Abstract
Lateral double-diffused metal-oxide-semiconductor (LDMOS) transistors are key interfaces between digital CMOS circuits and the real analog world; they are widely used in high-voltage and high-current applications, but they can be exceedingly difficult to model accurately. This article reviews recent advances in the compact modeling of LDMOS transistors, with an emphasis on the surface-potential-based high-voltage MOS (SP-HV) model and its capabilities. Detailed physical analysis of experimentally observed complexities in LDMOS behavior are reviewed and the relevance to IC design of the advanced modeling capabilities of SP-HV are detailed.
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