4H-SiC layer with multiple trenches in lateral double-diffused metal-oxide-semiconductor transistors for high temperature and high voltage applications

Abstract

In this paper, we present a novel lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor for high-temperature and high breakdown voltage applications. The key idea in our study is replacing a 4H-SiC layer in a part of the buried oxide region (BOX) to reduce temperature effects. Moreover, the top of the 4H-SiC layer has multiple trenches to increase the breakdown voltage. These multiple trenches have been filled with an N-type silicon material. So, we call the proposed structures as multiple trenches 4H-SiC LDMOS (MTSiC-LDMOS). The proposed device is simulated by a two-dimensional ATLAS simulator, and we have shown that the maximum lattice temperature decreases and the breakdown voltage improves by optimization of multiple trenches in the 4H-SiC region. Also, the results show that the current flow and specific on-resistance have improved. Therefore, the MTSiC-LDMOS structure is more reliable than a conventional LDMOS (C-LDMOS) for high-temperature and high breakdown voltage applications.