Lateral Bipolar Transistor Research Articles

Model for a thin-film silicon-on-sapphire bipolar junction transistor

A silicon-on-sapphire lateral thin-film bipolar junction transistor is unique in that recombination on the interface between the overlying silicon dioxide layer and the silicon semiconductor underneath must be taken into account. A simplified model of recombination is developed and then applied to determine the recombination currents in the bulk of the base of a bipolar junction transistor and in adjacent space-charge regions. The expressions for these currents are used to modify the conventional Gummel–Poon model to include recombination on the top surface of a lateral bipolar junction transistor. In the modified form essential constants retain their original meanings.

Four quadrant multiplier core with lateral bipolar transistor in CMOS technology

A four quadrant multiplier core using lateral bipolar transistor in CMOS technology has been fabricated, tested and analysed. It has a high precision of linearity (with an error smaller than 2% for inputs over half of the power supply voltages), small offset of a few millivolts at the inputs, a small output offset of about 1.5 mV and a small dissipation.

Photon generation in forward-biased silicon p-n junctions

Photons are generated by forward biasing a silicon p-n junction at 10-5∼ 10-4quantum efficiency through radiative recombination. At large distances from the forward-biased junction, leakage currents of magnitudes significant for some VLSI circuits can appear due to the substrate minority carriers generated by the photons. The effective decay length of the measured leakage current is about several hundred to one thousand micrometers. The effects of forward biasing an input node or a parasitic lateral bipolar transistor are, therefore, longer ranged than commonly assumed.

Analysis of<tex>abla^2 phi - c^2 phi = g</tex>in a semi-infinite medium with an irregular boundary by means of network manipulators

A finite-difference method for finding the finite-power solution <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">\phi</tex> of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">\nabla^{2} \phi - c^{2} \phi = g</tex> in a semi-infinite medium with an irregular boundary is established. The method is radically different from the customary approach of simply truncating the medium in that the semiinfinite medium outside a strip that contains the irregular boundary is characterized by an operator-valued driving-point resistance and thereby removed from the first stage of the method. The solution within the strip is then determined by exploiting the theory of operator-valued finite ladder networks. Finally, the solution for the medium outside the strip is obtained by using the theory of infinite operator-valued ladder networks. This method is applied to a two-dimensional study of the minority-carrier density in the base region of a lateral bipolar transistor on a chip that is effectively infinitely deep so far as the transistor's behavior is concerned. The method is quite conservative of computer time.

Device characterization on monocrystalline silicon grown over SiO2by the ELO (epitaxial lateral overgrowth) process

MOS and lateral bipolar transistors have been fabricated on epitaxial silicon layers which have been laterally overgrown over SiO 2 . These device characteristics were than compared to those measured on devices fabricated on homoepitaxial silicon and bulk silicon. The measurements indicate essentially identical MOS device characteristics for all three materials with a typical hole field effect mobility of about 180 cm2/vs. Lifetime measurements using pulsed C-V techniques showed essentially the same values for ELO material and homoepitaxial material with the ELO value being about 20 µS for 1015cm-3doping level. These lifetime values correlate will with diode and bipolar transistor measurements.

A new carrier-domain mangnetometer

A rotating-carrier-domain magnetic-field sensor with zero threshold field is presented. The device is circular lateral bipolar transistor surrounded by four voltage probing contacts. In contrast to previous carrier-domain magnetometers with four-layer, thyristor-like structures, the present sensor has three layers, the crucial circular structure being determined by a single mask. The device operates in the collector-emitter breakdown regime with short-circuited emitter and base contacts. It is based by an external constant current source. If the current supplied to the collector is above a certain threshold value, a localized current domain develops in the base region and rotates spontaneously, even at zero magnetic field, with constant tangential velocity. The angular frequency of the carrier-domain rotation is modulated by a magnetic field perpendicular to the planar device surface. Sensitivity around zero field is 250 kHz/T. The over-all plot of the rotation velocity versus the magnetic field shows a hysteresis loop. The device behaviour is explained in terms of the temperature dependence of emitter-collector breakdown phenomena and the Lorentz force acting on the current domain.

An analytical breakdown model for short-channel MOSFET's

Avalanche-induced breakdown mechanisms for short-channel MOSFET's are discussed. A simple analytical model that combines the effects due to the ohmic drop caused by the substrate current and the positive feedback effect of the substrate lateral bipolar transistor is proposed. It is shown that two conditions must be satisfied before breakdown will occur. One is the emission of minority carriers into the substrate from the source junction, the other is sufficient avalanche multiplication to cause significant positive feedback. Analytical theory has been developed with the use of a published model for short-channel MOSFET's. The calculated breakdown characteristics agree well with experiments for a wide range of processing parameters and geometries.

VIB-2 lateral pnp GaAs bipolar transistor with minimized substrate currents

VIB-2 lateral pnp GaAs bipolar transistor with minimized substrate currents

Lateral pnp GaAs bipolar transistor prepared by ion implantation

A lateral pnp bipolar transistor structure has been realised in n-GaAs material using ion implantation. Be ions have been implanted to form the emitter and collector. Proton implantation has been used to reduce the area of the parasitic emitter-substrate diode. First results of a transistor with a current gain of 0.5 are shown.

A Magnetic Sensor Utilizing an Avalanching Semiconductor Device

A new semiconductor device for sensing uniaxial magnetic fields has been realized. The device is basically a dual-collector open-base lateral bipolar transistor operating in the avalanche region, and is referred to as a Magnetic Avalanche Transistor. It exhibits high magnetic transduction sensitivity compared to traditional Hall-effect and conventional nonlinear magnetoresistive devices. Several hundred experimental devices have been designed, fabricated, and tested over the past two years. Many structural and some process parameters were varied. The magnetic sensitivity of a typical device was found to be proportional to substrate resistivity. A sensitivity of 30 volts per tesla was measured for devices which used 5-ohm-cm p-type substrates. The output signal measured between collectors is differential and responds linearly with field magnitude and polarity. A typical signal-to-noise ratio is 20,000 per tesla. The bandwidth is known to extend well beyond 5 MHz. The sensitive area is calculated to be on the order of 5 µm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . This communication describes the basic structure, fabrication, and characteristics for the magnetic avalanche transistor.

Electrical properties of silicon-implanted furnace-annealed silicon-on-sapphire devices

The crystalline quality of s.o.s. layers can be improved near the silicon-sapphire interface by silicon implantation followed by recrystallisation. Device performance on such layers is markedly improved as to n-channel m.o.s.t. noise and leakage current, reverse diode current and lateral bipolar transistor gain. Minority-carrier lifetimes up to 50 ns are deduced.