Lateral Bipolar Transistor Research Articles

Realising high-current gain p-n-p transistors using a novel surface accumulation layer transistor (SALTran) concept

The authors report a new p-n-p surface accumulation layer transistor (SALTran) on SOI, which uses the concept of surface accumulation of holes near the emitter contact to significantly improve the current gain. Using two-dimensional simulation, the performance of the proposed device has been evaluated in detail by comparing its characteristics with those of the previously published conventional p-n-p lateral bipolar transistor (LBT) structure. From the simulation results it is observed that, depending on the choice of the emitter doping and the emitter length, the proposed SALTran exhibits a current gain enhancement of around twenty times that of the compatible lateral bipolar transistor, without deteriorating the cutoff frequency. Reasons for the improved performance of the SALTran are discussed, based on these detailed simulation results.

Analysis and design of the dual-gate inversion layer emitter transistor

The dual-gate inversion layer emitter transistor (DGILET) is a device in which the injection of minority carriers takes place from an inversion layer formed under a MOS gate. Therefore, the device can be switched between MOS and bipolar modes using the gate giving the means to achieve a superior combination of low conduction losses and low switching losses. The structure of the device and operation in both the unipolar and bipolar modes are described in detail. Devices have been fabricated on bulk silicon wafers using junction isolation and experimental results confirm the expected superior performance. In particular, the results confirm predictions that if the inversion layer injector is properly designed, the voltage snapback that occurs during the transition between unipolar and bipolar modes can be completely suppressed. This can be achieved with a compact structure in contrast to the extended structures required in anode-shorted lateral insulated gate bipolar transistor (LIGBTs). An equivalent circuit for the DGILET is presented and the control of the minority carrier injection is also analyzed. Experimental results show that the DGILET can switch at speeds approaching those characteristic of MOSFETs with operating current densities comparable to LIGBTs. The results show that the DGILET offers lower overall losses than an LIGBT at switching frequencies above about 10 kHz.

Radiation-induced base current broadening mechanisms in gated bipolar devices

Ionizing radiation experiments on gated lateral bipolar junction transistors (BJTs) show a broadening in the peak base current profile after irradiation. The primary mechanism for this effect is identified as the change in the charge state of interface traps in the oxide over the base. Simulations and theoretical analysis not only describe the mechanism in detail, but also suggest possible solutions for extracting information from the shape of the profile. The effects of the interface-trap energy distribution are investigated, showing that traps between flatband and threshold contribute to the width of the base-current peak.

Experimental measurements and 3D simulation of the parasitic lateral bipolar transistor triggering within a single finger gg-nMOS under ESD

The aim of this study is to propose an analysis of the parasitic lateral bipolar triggering into a single finger grounded gate n-MOS transistor under Transmission Line Pulse (TLP) stress. The experimental values are compared to numerical results issued from 3D simulation. Emission Microscopy for Multi-layer Inspection (EMMI) views and physical extractions for analysis during this electrical stress reveal similar results. Thus, it appears that the triggering is different for two ElectroStatic Discharge (ESD) current levels.

A low-cost horizontal current bipolar transistor (HCBT) technology for the BiCMOS integration with FinFETs

A novel Horizontal Current Bipolar Transistor (HCBT) is processed with the scaled down dimensions and the improved technology. The active transistor region is built in the defect-free sidewall of the 580 nm wide n-hills in the (1 1 0) wafer, implying the reduction of the parasitic region's volume, i.e. the extrinsic base and the collector. The fabricated HCBT exhibits the cutoff frequency ( f T) of 21.4 GHz, the maximum frequency of oscillations ( f max) of 32.6 GHz and the collector–emitter breakdown voltage (BV CEO) of 5.6 V, which are the highest f T and the highest f TBV CEO product among the lateral bipolar transistors (LBTs).

Lateral SiGe heterojunction bipolar transistor by confined selective epitaxial growth: simulation and material growth

A new design for a lateral SiGe HBT has been based on development studies of confined lateral selective epitaxial growth in cavities built into silicon-on-insulator wafers. A design process is described and modelled. Device simulations indicate devices with maximum f T of 22 GHz with peak gain of 95 and f max of 14 GHz can be obtained by the processes outlined. The simulation results highlight the feasibility of the design and further improvements and scaling of the device would allow the transistor to operate at even higher frequencies and lower power.

Origin of 1/ f noise in lateral PNP bipolar transistors

1/ f noise was measured on lateral bipolar PNP transistors over a temperature range of 220< T<450 K. Noise power spectral density measurements were performed simultaneously across two resistors connected in series with base and collector. The equivalent base current noise source S I B has two dominant components. One is S I BE that is between the base and the emitter, in parallel with r π . The other is S I BC coming from the surface recombination current at the neutral base, between the base and the collector. The extracted S I B exhibited a near square law dependence on base current I B. The noise remained nearly constant when the temperature was below 310 K. However, it presented strong temperature dependence when the temperature was beyond 310 K. Two different models are proposed for the noise in different temperature regions. For the high temperature region, the surface recombination velocity fluctuation model is proposed, which indicates that the noise is coming from the fluctuations in the surface recombination velocity at the neutral base surface. The tunneling assistant trapping model is responsible for the low temperature region, where the noise source is the carrier trapping–detrapping by the defects in the spacer oxide covering the surface of the depletion layer.

Accurate current sensor for lateral IGBT smart power integration

This paper describes research work on the design and fabrication of a current sensor suitable for smart power integration in lateral insulated-gate bipolar transistor (LIGBT) structure. In general, the proposed design can also be used for various types of MOS-controlled bipolar transistor structures. Both the electron and hole current sensor layers are integrated in a concise form within the device structure. The sensing performance was further refined with the proposed flat-top doping profile achievable through a double-implantation, single-anneal and post-anneal-oxidation approach. The integrated structure was fabricated on silicon wafer with laboratory measurements performed to verify its electrical performance. The sensing ratio is maintained at a relatively constant level with a variation of within /spl plusmn/0.46% and /spl plusmn/1.2% (as a switching device), and /spl plusmn/0.85% and /spl plusmn/1.73% (as an amplifier device), respectively, when anode current and gate voltage vary. For operating temperature range of 300 K to 400 K, the sensor is able to maintain a sensing ratio within /spl plusmn/5.2% variation.

Micropower low-voltage analog filter in a digital cmos process

Techniques for implementing micropower analog filters using digital CMOS process technology are described. PMOS devices operating in accumulation are used for the integration capacitors, and the voltage swing across them is limited by employing current-mode operation using the log domain approach. The latter is implemented using enhanced lateral bipolar transistors. A second-order low-pass filter with a cutoff frequency of 22 kHz, fabricated in a 0.25-/spl mu/m digital CMOS technology, consumes 4.1 /spl mu/W from a 1.5-V supply and has an rms output noise of 0.25 nA. The filter's signal-to-noise ratio at 1% total harmonic distortion (THD) is 56 dB and its maximum S/(N+THD) is 45 dB. The chip occupies 0.085 mm/sup 2/.

Analysis of the thin-film SOI lateral bipolar transistor and optimization of its output characteristics for high-temperature applications

In this paper, we investigate and optimize the static characteristics of NPN lateral bipolar transistors implemented in a thin-film fully-depleted SOI CMOS process for high-temperature analog applications. The basic lateral SOI bipolar device, which shows good behaviour in high-temperature circuits in spite of its relatively poor performances, is firstly described regarding its process and layout parameters. Then the concept of the graded-base bipolar transistor is introduced. This device presents significantly improved output characteristics while preserving standard current gain and CMOS process compatibility. Measurements and simulations are used to demonstrate the improvements of the breakdown voltage and the Early voltage of the bipolar device.

Analysis on high-frequency characteristics of SOI lateral BJTs with self-aligned external base for 2-GHz RF applications

High-frequency characteristics of SOI lateral BJTs designed for 2-GHz radio frequency (RF) applications are measured and compared for various link-base length, emitter width, and collector structure. Based on experimental data and device simulation, degradation mechanism of cutoff frequency for shorter link-base is analyzed. By suppressing external base-induced effects, peak cutoff frequency is increased from 10 GHz to 15 GHz.

Substrate-triggered ESD clamp devices for use in power-rail ESD clamp circuits

New electrostatic discharge (ESD) clamp devices for using in power-rail ESD clamp circuits with the substrate-triggered technique are proposed to improve ESD level in a limited silicon area. The parasitic n–p–n and p–n–p bipolar junction transistors (BJTs) in the CMOS devices are used to form the substrate-triggered devices for ESD protection. Four substrate-triggered devices are proposed and investigated in this work, which are named as the substrate-triggered lateral BJT, the substrate-triggered vertical BJT, the substrate-triggered double BJT, and the double-triggered double BJT. An RC-based ESD-detection circuit is used to generate the triggering current to turn on the proposed substrate-triggered devices. In order to trigger on the parasitic bipolar transistors more effectively, the symmetric multiple-cell square-type layout method is used to realize these substrate-triggered devices. The power-rail ESD clamp circuits with such substrate-triggered devices have been fabricated in a 0.6-μm CMOS process. Experimental results have shown that the substrate-triggered device with double-BJT structure can provide 200% higher ESD robustness in per silicon area, as compared to the NMOS with the traditional gate-driven design.

Total-dose effects in double-gate-controlled NPN bipolar transistors

The sensitivity to radiation-induced degradation of new double-gate-controlled lateral NPN bipolar transistors has been investigated. The radiation hardness is improved when the device is working in the accumulation mode. The effect of positive charge and increased surface recombination velocity is analyzed by means of device simulations and experimental results.

Low-frequency noise in TFSOI lateral n-p-n bipolar transistors

Low-frequency (1/f) noise is characterized as a function of base current density (J/sub B/) on thin-film-silicon-on-insulator (TFSOI) lateral bipolar transistors. In the low injection region of operation, the noise power spectral density was proportional to J/sub B//sup 1.8/ for J/sub B/ 0.4 /spl mu/m/sup 2/), the noise bias dependence shifts to J/sub B//sup 1.2/, indicating current crowding effects, alter the contribution of noise sources near the extrinsic base link region of the device. In addition to the expected 1/f noise and shot noise, we have observed a bias dependent generation-recombination (Gm) noise source in some of the devices. This G/R noise is correlated to random-telegraph-signal (RTS) noise resulting from single trapping centers, located at or near the spacer oxide and/or the Si to SIMOX interface, which modulate the emitter-base space charge region.

A SOI LDMOS technology compatible with CMOS, BJT, and passive components for fully-integrated RF power amplifiers

This paper presents a silicon-on-insulator (SOI) lateral double-diffused MOS transistor (LDMOS) technology, which is compatible with complementary metal oxide semiconductor (CMOS), lateral bipolar junction transistor (BJT), and passive components for the implementation of radio frequency (RF) fully-integrated power amplifiers (IPAs) used in wireless communications. This technology allows complete integration of the low-cost and low-power front-end circuits with the baseband circuits for single-chip wireless communication systems. The SOI LDMOS transistor (0.35 /spl mu/m channel length, 3.85 /spl mu/m drift length, 4.5 GHz f/sub T/, and 20 V breakdown voltage), CMOS transistors (1.5 /spl mu/m channel length 0.8/-1.2 V threshold voltage), lateral BJT (18 V BV/sub CBO/, and 6.4 V BV/sub CEO/) and high Q-factor (up to 6.1 at 900 MHz and 7.2 at 1.8 GHz for an inductance of 7 nH) on-chip inductor are designed and fabricated to show the feasibility of the IPA implementation. A fully functional high performance integrated power amplifier for 900 MHz wireless communication transceivers is also demonstrated.

Trade-off between the Kirk effect and the breakdown performance in resurfed lateral bipolar transistors for high voltage, high frequency applications

The trade-off between the breakdown performance and the Kirk effect has been evaluated and compared among conventional bipolar transistors and resurfed lateral bipolar transistors. It was demonstrated that the traditional conflict of differing requirements on W c and N c by the breakdown performance and the Kirk effect can be eased by incorporating the resurf principle. Comparative studies have been carried out between the optimized devices with breakdown voltages from 20 to 40 V. It is shown that for an identical breakdown voltage, the high-current-level performance of the resurfed devices can be significantly improved by incorporating a gradually doped collector region. This further leads to a significant increase in the cut-off frequency without degrading the breakdown performance.

A novel lateral bipolar transistor with 67 GHz f/sub max/ on thin-film SOI for RF analog applications

In this paper, a novel lateral bipolar transistor on thin film silicon-on-insulator (SOI) is presented. With a small emitter size of 0.12/spl times/3.0 /spl mu/m/sup 2/, low base resistance of 270 /spl Omega/ due to a novel Co silicided base electrode and low base-collector parasitic capacitances of 1.4 fF due to SOI material, it achieves the highest f/sub max/ of 67 GHz among SOI bipolar transistors. Also, the low emitter-base capacitance of 1.5 fF and the low collector-substrate capacitance of 2.5 fF are realized. The transistor has a simple structure, which is fabricated with simplified processes without any new sophisticated technologies, excluding trench isolation and epitaxial base used in current bipolar transistors. This can lower the fabrication cost of transistors. We have demonstrated the possibility of lateral bipolar transistor on thin film SOI as next-generation device for RF analog applications.

Dynamic latch-up in advanced LIGBT structures at high operating temperatures

Abstract The dynamic latch-up process in conventional and modified lateral insulated gate bipolar transistor (LIGBT) structures is studied in this paper. In a previous study, we have argued that the modified structure shows a superior static latch-up performance at high operating temperatures. The dynamic latch-up has also been measured under resistive load at different operating temperatures. The dependence of the dynamic latch-up current with the gate resistance has also been taken into account. A figure of merit of the dynamic latch-up current normalized to the static latch-up current level as a function of operating temperature shows the excellent electrical behaviour of the proposed modified LIGBT structure at high temperatures when compared with its conventional counterpart.

On the design and fabrication of novel lateral bipolar transistor in a deep-submicron technology

The performance of a npn Lateral Bipolar Transistor (LBJT), based on a minimally modified submicron MOSFET without gate oxide, was studied by means of simulations and measurements on fabricated devices. Large-tilt angle, single-sided implants were successfully used to control the breakdown voltage by tailoring an asymmetric collector doping profile and providing a lightly doped region on the collector side to increase the breakdown voltage. This was accomplished by using a base/gate pedestal as the mask for the large-tilt angle, single sided implantation in a self-aligned fashion. The individual collector–base and emitter–base junctions were found to be of excellent quality but, as expected due to the lack of carrier confinement in the base of devices built on bulk silicon, the common emitter current gain was lower than one. Two options enhancing the device performance were studied using simulators: building the LBJT on Silicon-on-Insulator (SOI) or introducing SiGe into the base. The SOI device promises to provide better performance and ease of processing when compared to the SiGe base device.

A novel multi-cell lateral insulated gate bipolar transistor in the DELDI technology

In this paper, a planar, multi-cell Lateral Insulated Gate Bipolar Transistor (MCLIGBT) in the Double Epitaxial Layer Dielectric Isolation (DELDI) technology is proposed. This novel device exhibits a quasi-vertical mode of operation to achieve a localized conductivity modulation in the sandwich region between the adjacent cathode cells. Detailed numerical analysis shows that the Kirk effect plays an important role in achieving such a localized conductivity modulation and a significantly enhanced on-state performance is achievable without affecting its switching and blocking capability. Furthermore, this device does not require additional fabrication steps to an existing high voltage CMOS process and, therefore, is highly cost and area efficient.