Latch-up Characteristics Research Articles

Characteristics of latch-up current of dose rate effect by laser simulation

Due to the parasitic PNPN structure, the complementary metal oxide semiconductor (CMOS) integrated circuit may be affected by the latch-up effect, and the latching induced by the transient high dose rate Gamma ray has unique characteristics. In order to explore the complex physical mechanism of the latch-up by transient dose rate effect, in this paper we select the pulsed laser with 1064 nm wavelength as an radiation source to simulate the gamma ray radiation environment, select bulk silicon CMOS deserializer FIN1218MTDX, and use transient dose rate effect laser simulation experiments to explore its latch-up threshold and latch-up current characteristics. The test obtains that the dose rate latch-up threshold optical power density of the device at 3.3 V operating voltage is (8.5 ± 1.2) × 10<sup>4</sup> W/cm<sup>2</sup>, a latch-up voltage of the device is 2.8 V, only the device latches when the supply voltage is greater than 2.8 V. At the same time, it is found that under the working voltages of 3.3 V and 3.6 V and the optical power density between 1.9 × 10<sup>6</sup> W/cm<sup>2</sup> and 1.6 × 10<sup>7</sup> W/cm<sup>2</sup>, the latch-up current significantly decreases, the latch-up current " window phenomenon” appears. Based on the equivalent circuit model, the multi-path latching mechanism is used to construct the HSPICE model. The mechanism of the transient dose rate latching characteristics exposed by the laser test is analyzed by circuit-level simulation. The results show that the latch-up current and the latch-up voltage are related to its own latch structure when the device is latched. The phenomenon of latch-up current window in laser test is due to the multi-path latch mechanism, which will be in the specific circuit structure, and causing the multiple latch-up paths of the device to be switched. The reason of the latch-up path is switched is that the different holding voltages and trigger conditions between the latch-up paths, distributed resistance in the circuit reduces the voltage of latch-up path, so that the holding voltage of the latch-up path cannot be satisfied and the latch-up path is released. At the same time the other latch-up path is latched.

Effect of Misfit Dislocations in Junctions and Base Thickness on Latch-up Characteristics in Two-Terminal Vertical Thyristor-Based Capacitorless Memory

Conventional dynamic random access memory (DRAM) has been facing a severe challenge to scale down to 10 nm size. The cell capacitor should be able to store sufficient charges of 25~30 fF/cell. In order to meet this requirement, high aspect ratio of cell capacitor is inevitable, resulting in capacitors leaning into each other. To overcome this issue coming from capacitor, the vertical thyristor-based two-terminal capacitorless memory was proposed as a promising candidate to replace current DRAM, which consists of p++-anode / n+-base / p+-base / n++-cathode vertical structure using conventional Si technology. The two-terminal vertical thyristor-based capacitorless memory cell having p++-anode / n+-base / p+-base / n++-cathode vertical structure is easy to construct cross-point memory array cells, as shown in Figure 1. Furthermore, Two-terminal vertical thyristor-based capacitorless memory array cells can be operated without selector since sneak current is suppressed by latch-down process. In our study, three types of two-terminal vertical thyristor-based capacitorless memory cells consist of top-p++-anode / n+-base / p+-base / bottom-n++-cathode with 80-nm-thick base region (PNPN80), top-p++-anode / n+-base / p+-base / bottom-n++-cathode with 160-nm-thick base region (PNPN160), and top-n++-cathode / p+-base / n+-base / bottom-p++-anode with 160-nm-thick base region (NPNP160) were fabricated, individually. The dopant concentration profile of each device was analyzed by secondary ion mass spectroscopy (SIMS), as shown in Figure 2. By correlating HR TEM images with SIMS analyses, misfit dislocations were observed at the depth where dopant pile-up was found, as shown in Figure 3. Figure 4 (a), (b) and (c) show I-V measurements of PNPN80, PNPN160 and NPNP160, respectively. The difference of latch-up voltages between Figure 4 (b) and (c) can be explained by carrier life-time difference. NPNP160 had less misfit dislocations compared to PNPN160, resulting in longer excess carrier life-time, since dislocations act as recombination centers. Thus, NPNP160 needed smaller anode voltage to induce sufficient excess carriers in base regions, which had smaller latch-up voltage than PNPN160. In addition, the difference of latch-up voltages between Figure 4 (a) and (b) resulting from base thickness difference can be explained by electric field. The electric field of PNPN160 is weaker than that of PNPN80 in base regions when equivalent anode voltage is applied. Therefore, PNPN160 needed larger anode voltage to lower the injection barrier of excess carriers. Besides, the effect of misfit dislocations and base dopant concentration on memory margin and off-state leakage current will be discussed. Finally, the memory cell pulse operations will be exhibited as well. Acknowledgment * This research was supported by Brain Korea 21 PLUS Program in 2018, the MOTIE (Ministry of Trade, Industry & Energy 10069063) and KSRC (Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device. Figure 1

SCR-Based ESD Protection Using a Penta-Well for 5 V Applications

This paper proposes a new structure of silicon controlled rectifier (SCR)-based ESD protection circuit using a penta-well for ESD protection in 5 V applications. The proposed circuit exhibits higher holding voltage and current-driving capability than low Ron SCR (LRSCR) ESD protection circuits. The existing LRSCR ESD protection circuit and the proposed ESD protection circuit were fabricated using the 0.18 $\mu$ m BCD process. The electrical and latch-up characteristics were compared and analyzed using transmission line pulse measurement and a transient-induced latch-up test.

Investigation of Electrical Latchup and SEL Mechanisms at Low Temperature for Applications down to 50K

This paper presents a physical investigation of the mechanisms induced by the low temperature on single-event latchup in CMOS inverters for a range of technology nodes (250 nm from Sofradir and 180 nm from IBM). For the first time, the TCAD simulations show a good agreement of latchup characteristics with the experimental measurements at cryogenic temperatures. Additionally, a more robust technology provided by Sofradir was demonstrated.

ESD and Latchup Optimization of an Embedded-Floating-pMOS SCR-Incorporated BJT

This paper develops optimization between electrostatic discharge (ESD) and latchup characteristics for a silicon-controlled rectifier (SCR)-incorporated Bipolar Junction Transistor (BJT) in a 0.18- $\mu \text{m}$ , 3.3 V process. This device is composed of a floating pMOSFET embedded in a parasitic n-well/p-sub/n+ region BJT structure. The floating pMOS gate is further coupled with an RC network for controlling its switching. The floating pMOS could increase the effective width of its floating p+ region to enhance ESD robustness during ESD zapping events, whereas maintain its floating p+ region narrower during IC operation situation. With the optimized structure dimensions, this device can reach transmission-line pulse second breakdown current 6 A, ESD/ human-body model over 8 kV, which are the same as those of an SCR, and its latchup trigger current is at least 1.9 times greater.

200 V Superjunction N-Type Lateral Insulated-Gate Bipolar Transistor With Improved Latch-Up Characteristics

This paper evaluates the technique used to improve the latching characteristics of the 200 V n-type superjunction (SJ) lateral insulated-gate bipolar transistor (LIGBT) on a partial silicon-on-insulator. SJ IGBT devices are more prone to latch-up than standard IGBTs due to the presence of a strong pnp transistor with the p layer serving as an effective collector of holes. The initial SJ LIGBT design latches at about 23 V with a gate voltage of 5 V with a forward voltage drop (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> ) of 2 V at 300 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The latch-up current density is 1100 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The latest SJ LIGBT design shows an increase in latch-up voltage close to 100 V without a significant penalty in V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> . The latest design shows a latch-up current density of 1195 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The enhanced robustness against static latch-up leads to a better forward bias safe operating area.

Publisher's Note: “A Small-Sized Lateral Trench Electrode Insulated Gate Bipolar Transistor for Improving Latch-up and Breakdown Characteristics”

Publisher's Note: “A Small-Sized Lateral Trench Electrode Insulated Gate Bipolar Transistor for Improving Latch-up and Breakdown Characteristics”

SEE characteristics of small feature size devices by using laser backside testing

This paper presents single event upset (SEU) and single event latch-up (SEL) characteristics of small feature size devices by laser backside testing method, which is dedicated to dealing with the increasing metal layers on the front side of integrated circuits. The influence of test data pattern on SEU threshold and cross-section is investigated. The supply current state of micro latch-up for deep sub-micron SRAM is described. The laser energy thresholds were correlated to heavy ion thresholds LET to determine an empirical relationship between laser energy threshold and heavy ion LET. This empirical relationship was used to estimate the equivalent laser LETs for devices fabricated in small feature sizes. Moreover, the SEU of a Power PC CPU fabricated with 90 nm SOI CMOS process has been tested, which indicates that the laser backside method could be used to evaluate SOI small feature size devices.

Simulation of a new lateral trench IGBT employing effective p+ diverter for improving latch-up characteristics

A new lateral trench insulated gate bipolar transistor (LTIGBT) with p+ diverter was proposed to improve the characteristics of the conventional LTIGBT. The p+ divert layer was placed between the anode electrode and the cathode electrode. Generally, as the conventional LTIGBT had a p+ divert region, the forward blocking voltage was decreased greatly because the n-drift layer corresponding to the punch-through region was reduced. However, the forward blocking voltage of the proposed LTIGBT with p+ diverter was about 140V. That of the conventional LTIGBT of the same size was 105V. Because the p+ diverter region of the proposed device was an enclosed trench oxide layer, the electric field moved toward the trench-oxide layer, and punch through breakdown of LTIGBT with p+ diverter occurred. Therefore, the p+ diverter of the proposed LTIGBT did not relate to breakdown voltage in a way different to the conventional LTIGBT. The latch-up current densities of the conventional LTIGBT and LTIGBT with p+ diverter were 540, and 1453A/cm2, respectively. The enhanced latch-up capability of the proposed LTIGBT with p+ diverter was obtained through holes in the current directly reaching the cathode via the p+ divert region and the p+ cathode layer beneath the n+ cathode layer.

Analysis of dual-gate LIGBT with gradual hole injection

The device characteristics of a gradual hole injection dual-gate lateral insulated gate bipolar transistor (GHI-LIGBT) is analyzed with the experiment and two-dimensional (2-D) numerical simulation. The hole injection mechanism in the GHI-LIGBT is investigated in detail and the device characteristics of the GHI-LIGBT are studied in terms of the various device parameters such as the p/sup +/ injector length and the injection gate length. The hole injection characteristics and latch-up characteristics in the GHI-LIGBT are also presented as a function of temperature. The experimental results demonstrate that an on-state voltage drop in GHI-LIGBT is reduced by 1 V, compared with the conventional SA-LIGBT and the negative resistance regime is eliminated since the injection of holes is initiated at the lower anode voltage. It is also found that the low on-state voltage drop in the GHI-LIGBT can be achieved without sacrificing the inherent high switching speed in shorted anode (SA) LIGBT structures.

Trench cathode TIGBT with improved latch-up characteristics

A new TIGBT (Trench Insulated Gate Bipolar Transistor) with a trench cathode is proposed to suppress the latch-up which is a key problem to limit the maximum operating current. The efficiency of the proposed device is verified by numerical analysis with MEDICI. Trench cathode TIGBT could suppress the latch-up at anode voltage of 300 V and current density of 19 000 A/cm2 while planar IGBT and conventional TIGBT latch at the anode current density of 1300 and 4200 A/cm2, respectively. Forward voltage drops of trench cathode TIGBT, conventional TIGBT and planar IGBT are 1.53 V, 1.48 V and 2.43 V, respectively. In addition, trench cathode TIGBT has very large FBSOA (Forward Biased Safe Operating Area) compared with that of conventional TIGBT and planar IGBT.

Impact of geometrical scaling on parasitic pnp bipolar transistor in N-well, 0.25 μm CMOS devices and its effect on latchup immunity

This paper presents a detailed analysis of latchup dependence on geometrical dimensions of N-well, 0.25 μm complementary metal-oxide silicon (CMOS) devices with 50 Ågate oxide using simulation and experiment. Simulation results show that as dimensions continue to shrink, the traditionally accepted vertical parasitic pnp bipolar transistor becomes a lateral device. This observed result is very significant since increasing the N-well junction depth no longer guarantees improvement in latchup immunity. Experimental data shows that variation in p+ emitter to N-well edge spacing ( d plat) does not affect latchup characteristics as long as d plat is far greater than d pver, the difference between the N-well and p+ diffusion junction depth.

High energy ion implantation for profiled tub formation and impurity gettering in deep submicron CMOS technology

High energy ion implantation has been utilized to fabricate profiled tubs and to create gettering sites in deep submicron CMOS devices in bulk and epitaxial Si. The isolation and latch-up characteristics have been measured and found to be superior to those of devices in tubs fabricated by the conventional thermal drive-in method. High energy implants into bulk Si produce inferior gettering as deduced from diode leakage measurements. Iron gettering to the MeV boron implanted region has been investigated.

A Trench-Gate Silicon-on-Insulator Lateral Insulated Gate Bipolar Transistor with the p+ Cathode Well

A trench-gate silicon-on-insulator (SOI) lateral insulated gate bipolar transistor (LIGBT) with the p+ cathode well is proposed to improve the latch-up characteristics, and the improved characteristics are verified numerically by MEDICI simulation. It is found that the trench-gate SOI LIGBT exhibits at least 6 times larger latch-up capability than the conventional devices. The enhanced latch-up capability of the trench-gate SOI LIGBT is obtained due to the fact that the hole current in the device bypasses the resistance of the p body region which is the source of the latch-up and reaches the cathode via the p+ cathode well.

The modified structure of the lateral IGBT on the SOI wafer for improving the dynamic latch-up characteristics

The modified structure of the lateral IGBT(LIGBT) on an SOI wafer for improving the dynamic latch-up characteristics is presented together with its numerical simulations and experimental results. The modified LIGBT structure has a p/sup +/-emitter layer between the collector and gate regions. The current at which the latch-up occurs during the turn-off transient under an inductive load is estimated in comparison with that of the conventional LIGBT. The dynamic latch-up current at room temperature and 125/spl deg/C for the modified LIGBT were 350 A/cm/sup 2/ and 290 A/cm/sup 2/, respectively. These results indicate the improvement of about 3.5 times at room temperature and about 5.5 times at 125/spl deg/C compared with those for the conventional LIGBT. This remarkable improvement in the dynamic latch-up performance is accomplished at the expense of an increase of 0.8 V in the forward voltage drop.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A tool towards integration of IC process, device, and circuit simulation

An interactive simulation system, comprised of an integrated set of tools, suitable for accurate characterization of arbitrary submicrometer devices is presented. The system, which is an extension of the University of California, Berkeley, tool SIMPL-IPX, uses a transparent link with 2D device simulation and provides an application-specific interface to 3D. While the system can be used to generate typical device characteristics (I-V curves and delay analysis) useful for sensitivity analysis and analytic model development, a greater benefit of the system is its ability to analyze parasitic devices that may lead to reliability problems. These parasitic devices are extremely difficult to characterize and tend to be overlooked. The system is used to investigate the influence of these parasitics by analyzing the effect of layout on the latch-up characteristics of a standard logic cell. >

Characteristics of a new isolated p-well structure using thin epitaxy over the buried layer and trench isolation

An isolated p-well structure for deep-submicrometer BiCMOS LSIs is proposed. The structure consists of a retrograde p-well in an n-type thin epitaxial layer over an n/sup +/ buried layer, and trench isolation. Latchup characteristics in this CMOS structure and breakdown characteristics of the shallow p-well are studied on test devices. Excellent latchup immunity and sufficient voltage tolerance are obtained with a thin 1- mu m epitaxial layer. A CMOS 1/8 dynamic-type frequency divider using this well structure functions properly up to 3.2 GHz at a 2-V supply voltage. >

Transient latchup characteristics in n-well CMOS

Transient latchup characteristics in scaled n-well CMOS triggered by pulsewidths less than 10 ns are presented by experiments and two-dimensional device simulations. Vibratile increasing latchup currents predicted by the simulations are experimentally observed for the devices with the n/sup +/-p/sup +/ spacing L longer than 8 mu m, and twin-peaks curves in supply currents just before latchup turn-on are also measured. Those experimental results are in relatively good agreement with the simulations triggered by a trapezoidal pulse. It is also reported that CMOS latchup susceptibilities to narrow trigger-pulse widths of less than 50 ns cannot be expected as L becomes as short as about 4 mu m.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Analysis of d.c. and a.c. anomalous latch-up effects in commercial CMOS integrated circuits

Anomalous effects in electrical latch-up characteristics have been identified both in the d.c. (hysteresis effects) and a.c. (window effects) characteristics of a large sample of commercial CMOS ICs of different suppliers and technologies. Both d.c. and a.c. effects were always present in all tested devices which showed anomalies. Infra-red microscopy and scanning laser microscopy reveal that both effects are caused by current redistribution between different latch-up paths and are therefore correlated.

Infrared microscopy study of anomalous latchup characteristics due to current redistribution in different parasitic paths

Anomalous effects such as abrupt variations of the latchup current in steady-state conditions and window effects, i.e. the existence of a well-defined interval of I/O injected currents for latchup to occur, can occur during pulsed latchup tests. Infrared microscopy allows the correlation of electrical characteristics with latchup current distribution and reveals that anomalous effects are due to the dynamic competition between different latchup paths. This is confirmed by a SPICE simulation of the lumped equivalent circuit of a CMOS output comprising two coupled p-n-p-n parasitic structures.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>