Latchup Behavior Research Articles

A Revised Version of the ATLAS Tile Calorimeter Link Daughterboard for the HL-LHC

The ATLAS Tile Calorimeter (TileCal) readout link and control daughterboard (DB) is the central on-detector hub of the new TileCal electronics upgrade for the high-luminosity large hadron collider (HL-LHC). The DB, which has undergone gradual redesigns during development, provides the connection between the on- and off-detector electronics via bidirectional fiber-optic links. Two CERN-developed, radiation hard GBTx application specified integrated circuits (ASICs) receive LHC timing signals and configuration commands through 4.8-Gb/s downlinks, which are in turn propagated to the front end through Xilinx Kintex Ultrascale field-programmable gate arrays (FPGAs). The Kintex FPGAs also continuously perform real-time readout and transmission of digitized photomultiplier (PMT) samples, detector control system (DCS) signals, and monitoring data through redundant pairs of 9.6-Gb/s uplinks. The DB design aims at minimizing single points of failure and improving the performance and reliability of the board. Apart from the GBTx devices, the DB design relies on radiation-qualified commercial off-the-shelf (COTS) components. Mitigation of radiation-induced single-event upsets (SEUs) in the FPGAs is performed by a combination of the Xilinx soft error mitigation (SEM) controller and triple-mode redundancy (TMR) schemes in the FPGA firmware. Data integrity is protected through forward error correction (FEC) in the downlinks and cyclic redundancy check (CRC) error verification in the redundant uplinks. This article presents the latest revision of the DB (version 6), a redesign that addresses single-event latch-up (SEL) behavior observed in the Kintex Ultrascale+ FPGAs used in the previous revision, and features a more robust power circuitry combined with an improved current monitoring scheme, enhanced performance of the analog-to-digital converter (ADC) read-out, and improved timing performance.

High temperature / radiation hardened capable ARM® Cortex®-M0 microcontrollers

Abstract VORAGO Technologies has developed a pair of ARM Cortex M0 MCUs designed from the ground up to be high temperature capable. One of these devices is specifically developed for high temperature applications, the other adds capabilities that make it suitable for use in high radiation environments as well. These devices are fabricated using a modified version of commercial bulk 130nm CMOS technology utilizing our HARDSIL® technology, which provides immunity to the increased effects of latchup and EOS encountered at higher application temperatures. In addition to the processor these devices include features more typical of low temperature SoCs including on-chip memory, timers, and communications peripherals. In addition to the ceramic package and die format typically utilized at high temperature, a new lower-cost plastic package is available that has been characterized at higher temperatures. These devices have been characterized at temperatures up to 200C and results showing the latchup behavior and device performance are provided. Some of the tradeoffs involved in creating such devices are discussed, as well as some of the similarities and tradeoffs in creating a radiation hardened devices vs. a high temperature device.

Mechanisms and Temperature Dependence of Single Event Latchup Observed in a CMOS Readout Integrated Circuit From 16–300 K

Heavy ion-induced single event latchup (SEL) is characterized in a commercially available CMOS readout integrated circuit operating at cryogenic temperatures. SEL observed at 24 K and below is believed to be possible when free carriers produced by an ion strike initiate an exponential increase in the free carrier density via shallow-level impact ionization (SLII). This results in a large current increase that proceeds to a sustained latched state, even though the classic condition for parasitic bipolar gain product is not met since it is much less than unity. The LET threshold for SEL is significantly lower at 20 K as compared to 300 K although the saturated cross section is 2-3 times higher at 300 K. The temperature dependence of the SEL cross section is characterized from 16-300 K. SEL behavior attributed to the classical cross-coupled parasitic bipolar model is observed from ~135-300 K, and the reduction in the SEL cross section is remarkably modest as the temperature is lowered from room temperature to ~200 K. Temperature dependent electrical latchup characterization of a 130 nm pnpn test structure also indicates a change in the latchup behavior at ~50 K consistent with the SLII mechanism.

Explaining and eliminating latchup in a classical Wien oscillator via nonlinear design

A classical Wien-type sinusoidal oscillator is analyzed to explain the origin of its latchup behavior. Only when a correct nonlinear model of the oscillator is derived and the stability of all equilibrium points associated with each region of operation of the fundamentally nonlinear amplifier characteristics is studied can this phenomena be predicted. It is further shown how latchup can be eliminated.

Latchup characterization of 0.18-micron STI cobalt silicided test structures

The effects of varying both the Shallow Trench Isolation's (STI) dimension and geometrical spacings on latchup behavior for 0.18-μm cobalt silicided CMOS test structures were investigated. The as-developed characterization techniques and models aid in the optimization of device layout. The test data extracted for both the parasitic current gains and parasitic resistances over a range of layout dimensions were analyzed and modeled. The influence of biasing voltages on latchup reliability was also studied.

Matrix method for latch-up free demonstration in a triple-well bulk-silicon technology

A CMOS inverter made in bulk silicon by triple-well technology is examined with respect to its latch-up behavior. With this exemplary circuit and a matrix-like scheme it can be proved that the conditions for the occurrence of the latch-up effect are not met in any case. It is demonstrated that this type of technology leads to completely latch-up free CMOS circuits in bulk silicon and, therefore, extremely good hardness against transient radiation induced effects can be achieved without using SOI (silicon on insulator) and SOS (silicon on sapphire). Improved insensitivity to SEU (single event upset) can be expected. The existing paths between any of the distinguishable regions do not meet the requirements for the occurrence of latch-up.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Effects of the interaction of neighboring structures on the latch-up behavior of CMOS ICs

An experimental investigation on the interaction between different parasitic devices in CMOS ICs from the point of view of latchup triggering is outlined. The study, carried out by means of ad hoc test structures, shows that this interaction: (a) can lead to significant increase in latchup susceptibility; (b) can involve devices very distant from one another; and (c) is not always suppressed by guard ring protections. The main features of the experimental results are discussed and explained.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The effect of layout, substrate/well biases, and triggering source location on latchup triggering currents in bulk CMOS circuits

Based on the experimental measurement of latchup triggering currents, the effects of contact placements in wells, triggering source location and substrate/well bias on latchup immunity of p- n- p- n structures in bulk CMOS circuits are extensively investigated and characterized. From the measured triggering currents, latchup behavior due to external triggering sources can be more definitely understood. It is found that triggering current depends not only on the layout connections for a p- n- p- n structure but also, in most cases, strongly on the location of triggering sources as well as the substrate or well bias. An analytic model is derived to describe the dependence of the triggering current on the substrate or well bias. The substrate (well) triggering current is found to be linearly (linearly) dependent on the substrate (well) bias and to increase with increase of the well (substrate) bias.

The influence of the drain multiplication current on latchup behavior

A method is described for determining the maximum operating voltage of a NMOS transistor in a CMOS technology before latch-up occurs. The drain multiplication current and the shunting well resistance are very important parameters for simulating the initiation of the parasitic thyristor. Measurement results show the influence of the well resistance and the gate length for transistors processed on bulk wafers and on epi wafers. Good agreement between simulations and experimental results is obtained. >

Characteristics of CMOS devices in high-energy boron-implanted substrates

CMOS devices on substrates subject to high-energy implantation of boron for buried-layer fabrication are examined. FET device characteristics, threshold voltage, and breakdown characteristics are investigated, along with mobility and minority-carrier lifetime. In addition, well leakage and breakdown are studied in an effort to provide guidelines for well design in an megaelectronvolt-implanted substrate. It is seen that MOSFET transistor characteristics are virtually unaffected by the implant. Latchup behavior improves with the incorporation of the buried layer, and the holding voltage increases as the well and implant depths decrease.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A distributed model for radiation-induced latchup

A lumped-model approach is used to determine three-dimensional effects that often dominate latchup behavior in complex integrated circuits. A preprocessor is used that automatically generates a SPICE-compatible file of up to several thousand elements from a basic description of the topology and physics of local structures. The results show that internal potential drops in the substrate and isolation wells are much larger than the metallization resistance contribution for devices with asymmetrical topology. The work also shows that alterations in the back contact, such as partial removal of the central portion for backside laser simulation, increase lateral voltage drops in the substrate by more than one order of magnitude, substantially changing the latchup characteristics. The model can be used to calculate distributed potentials that are important for latchup and the latchup window effect and to determine the effect of metal shadowing or nonuniform carrier generation when laser simulation is used.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Two-dimensional numerical analysis of latchup in a VLSI CMOS technology

The latchup behavior of a VLSI CMOS technology using hybrid Schottky-ohmic contact sources and drains and a high resistivity substrate has been extensively studied via two dimensional numerical simulation. The modeling allows quantitative explanation of the triggering and sustaining behavior of such structures, as well as an accurate characterization of the influence of the various process and geometrical parameters on the resistance to latchup. The technology is compared to a corresponding low resistivity substrate (epi) CMOS technology.

Two-Dimensional Numerical Analysis of Latchup in a VLSI CMOS Technology

The latchup behavior of a VLSI CMOS technology using hybrid Schottky-ohmic contact sources and drains and a high resistivity substrate has been extensively studied via two dimensional numerical simulation. The modeling allows quantitative explanation of the triggering and sustaining behavior of such structures, as well as an accurate characterization of the influence of the various process and geometrical parameters on the resistance to latchup. The technology is compared to a corresponding low resistivity substrate (epi) CMOS technology.

Quasi-two-dimensional simulation of transient latchup effect in VLSI CMOS circuits

The transient latchup behavior of a typical n-well CMOS structure has been simulated using the program MEDUSA. A quasi-2D representation of the parasitic thyristor was developed by describing the vertical and lateral bipolar transistor paths with 1D numerical models. The dependence of latchup behavior on circuit layout and external stimuli as well as on doping profiles was investigated. Good agreement with experimental results was obtained showing that the two-dimensional nature of the latchup effect can sufficiently be taken into account by this approach and a realistic description of the circuit surrounding of the latchup path can be achieved. Computation costs, however, are much less compared to a rigorous 2D transient analysis. A simple RC network representation of the critical latchup path is derived which allows the estimation of the maximum achievable forward bias of the bipolar transistors caused by power-up transients.

Layout and bias considerations for preventing transiently triggered latchup in CMOS

This paper investigates several techniques for hardening CMOS curcuitry against transiently triggered latchup. Measurements of critical rise time are made on four variations of the p-n-p-n structure inherent to CMOS. For each structure the n-well and substrate shunt resistances are varied as is the substrate bias. These measurements are performed on both bulk and epi-samples using both topside and backside substrate contacts. Comparison of the parasitic bipolar transistors comprising the p-n-p-n structures reveals that differences in bipolar behavior do not completely explain the differences in p-n-p-n latchup behavior. Test results are used to rate the various hardening techniques.