Quasi-two-dimensional simulation of transient latchup effect in VLSI CMOS circuits

Abstract

The transient latchup behavior of a typical n-well CMOS structure has been simulated using the program MEDUSA. A quasi-2D representation of the parasitic thyristor was developed by describing the vertical and lateral bipolar transistor paths with 1D numerical models. The dependence of latchup behavior on circuit layout and external stimuli as well as on doping profiles was investigated. Good agreement with experimental results was obtained showing that the two-dimensional nature of the latchup effect can sufficiently be taken into account by this approach and a realistic description of the circuit surrounding of the latchup path can be achieved. Computation costs, however, are much less compared to a rigorous 2D transient analysis. A simple RC network representation of the critical latchup path is derived which allows the estimation of the maximum achievable forward bias of the bipolar transistors caused by power-up transients.