Critical charge model for transient latch-up in VLSI CMOS circuits

W Reczek,J Winnerl,W Pribyl

doi:10.1109/icmts.1989.39318

Critical charge model for transient latch-up in VLSI CMOS circuits

W Reczek, J Winnerl + Show 1 more

https://doi.org/10.1109/icmts.1989.39318

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Publication Date: Mar 13, 1989

Citations: 4

Affiliation: Siemens (Germany)

#VLSI CMOS Circuits #Model For Latch-up + Show 8 more

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Abstract

Experimental results and theoretical considerations on the critical charge model for latch-up in VLSI CMOS circuits are presented. The critical charge is constant, proportional to the trigger phase pulse height, and inversely proportional to the trigger pulse width. With these results it is possible to calculate the transient latch-up susceptibility of circuits due to periodic pulses, e.g. overshoot, undershoot, and glitches. >

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