Abstract
The ATLAS Tile Calorimeter (TileCal) readout link and control daughterboard (DB) is the central on-detector hub of the new TileCal electronics upgrade for the high-luminosity large hadron collider (HL-LHC). The DB, which has undergone gradual redesigns during development, provides the connection between the on- and off-detector electronics via bidirectional fiber-optic links. Two CERN-developed, radiation hard GBTx application specified integrated circuits (ASICs) receive LHC timing signals and configuration commands through 4.8-Gb/s downlinks, which are in turn propagated to the front end through Xilinx Kintex Ultrascale field-programmable gate arrays (FPGAs). The Kintex FPGAs also continuously perform real-time readout and transmission of digitized photomultiplier (PMT) samples, detector control system (DCS) signals, and monitoring data through redundant pairs of 9.6-Gb/s uplinks. The DB design aims at minimizing single points of failure and improving the performance and reliability of the board. Apart from the GBTx devices, the DB design relies on radiation-qualified commercial off-the-shelf (COTS) components. Mitigation of radiation-induced single-event upsets (SEUs) in the FPGAs is performed by a combination of the Xilinx soft error mitigation (SEM) controller and triple-mode redundancy (TMR) schemes in the FPGA firmware. Data integrity is protected through forward error correction (FEC) in the downlinks and cyclic redundancy check (CRC) error verification in the redundant uplinks. This article presents the latest revision of the DB (version 6), a redesign that addresses single-event latch-up (SEL) behavior observed in the Kintex Ultrascale+ FPGAs used in the previous revision, and features a more robust power circuitry combined with an improved current monitoring scheme, enhanced performance of the analog-to-digital converter (ADC) read-out, and improved timing performance.
Highlights
T HE high-luminosity large hadron collider (HL-LHC) program involves a series of upgrades to the accelerator aimed at increasing the instantaneous luminosity to at least five times the original design value
The disruption to data taking from the measured single-event latch-up (SEL) rates is not acceptable for HL-LHC running. This motivates a new DB design based on Kintex Ultrascale (KU) field-programmable gate arrays (FPGAs), which are more resistant to latch-up
The DB is a read-out link and control board serving as a hub to interface the front-end electronics of a Tile Calorimeter (TileCal) MD with the off-detector electronics
Summary
T HE high-luminosity large hadron collider (HL-LHC) program involves a series of upgrades to the accelerator aimed at increasing the instantaneous luminosity to at least five times the original design value. This upgrade will allow the LHC to increase the volume of collision data provided. To prepare for this, extensive R&D work is ongoing to ensure that the read-out electronics of the upgraded ATLAS detector [1] are capable of meeting the new HL-LHC requirements. Date of publication August 9, 2021; date of current version September 16, 2021.
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