An updated design of the read out link and control board for the Phase-2 upgrade of the ATLAS Tile Calorimeter.

Abstract

The ATLAS hadronic Tile Calorimeter (TileCal) is being upgraded for the High Luminosity Large Hadron Collider (HL-LHC). We present a redesign of the TileCal Phase II read out link and control Daughterboard (DB). The DB has a double redundant radiation tolerant design that will provide continuous high-speed readout of digitized data samples of $12$ photomultiplier channels each with two gains, while handling the timing, control and communication between the front-end and off-detector electronics, all over multi-gigabit optical links. Four SFP+ modules serve $4\times9.6$ Gbps uplinks and $2\times4.8$ Gbps downlinks, handled respectively by two re-programmable Kintex Ultrascale+ FPGAs and two CERN developed gigabit link ASICs (GBTx). Better high-speed uplink timing and improved radiation tolerance have been achieved by migrating the previous design from the Xilinx Kintex-7 FPGAs to the Kintex Ultrascale+ architecture. Preliminary TID radiation tests were performed on a Daughterboard revision 5 following the TOTAL DOSE STEADY-STATE IRRADIATION TEST METHOD ESCC22900 and the ATLAS protocol and safety factors.