Latch Stage Research Articles

A dynamic power-efficient 4 GS/s CMOS comparator

This paper proposes a mid-stage latch circuit to be employed in a high-speed comparator. The advantages of the proposed circuit are low kickback noise and offset. Moreover, low-power and high-speed characteristics are obtained by avoiding direct connection between the pre-amplifier and latch stages using another stage between them. The power-delay product (PDP) of the comparator is reduced due to the reduction in charging and discharging delays at the latching nodes. The proposed comparator consumes only 244.19 µW using a 1 V supply voltage. Furthermore, the bandwidth, delay, offset, and kickback noise of the proposed comparator are 4 GHz, 26.91 ps, 3 mV, and 38 mV, respectively. Results indicate the proper performance of the proposed comparator in low-power applications.

A Review of Innovative Comparator Designs

Three papers on the optimal design of comparator circuits are further analyzed in this work. Each paper presents a method to improve the performance of comparators. Floating inverter amplifier applied an independent capacitor as the source of the preamplifier, which improves the overall performance of the circuit. In another design, a special local clock generator is proposed to control the input of both of the latch stage and the preamplifier, which makes it possible to adjust the speed and improve the energy efficiency. In dynamic bias circuit design, stabilized common-mode voltage is realized by adding a capacitor to the tail of the pre-amplifier of a latch-type comparator, optimizing the power and noise performance successfully.

Design of Low-Power High-Speed Double-Tail Dynamic Comparator Based on Charge-Steering Concept

In this thesis, a low-power dissipation high-speed double-tail dynamic comparator is designed. Based on the principles of charge-steering, a clock charge pump is used at the tail of the latch stage to replace the clock current source, which reduce the output swing and kick-back noise of the comparator. Meanwhile, digital logic is added to the pre-amplification stage to eliminate quiescent current and further reduce power consumption. Based on the SMIC 28nm CMOS process, the proposed comparator is simulated and verified. The results show that under the condition of 0.9V supply voltage and 1MHz sampling frequency, the power dissipation is 5.4μW, the delay is 245ps, and the offset voltage is 6.9mV. Compared with a high-speed comparator, under the premise of achieving the same performance, the power consumption is reduced by 69%.

Implementation and Optimization of CNTFET Based Ultra-Low Energy Delay Flip Flop Designs

Energy conservation and delay minimization are the two major goals while designing ultra-low-power digital integrated circuits at lower technology nodes. Here, silicon based carbon nanotube field effect transistor (CNTFET) has been explored as a novel material for future electronics design applications (EDA). In this paper, two energy-efficient switching activity minimization techniques have been applied with proposed designs. First technique detects the completion of sensing stage operation known as transition completion detection (TCD) technique. TC signal generated from NAND operation of complementary outputs of sensing stage which minimizes glitches in the complementary outputs of the latch stage. Another clock gating mechanism applied at the latch stage to smoothen the output waveforms Q and \(\overline {Q}\). The proposed and existing designs simulated using 32nm CMOS and 32nm CNTFET technology, indicating that the CNTFET based design reduces power by 45% and 36% respectively in comparison with conventional CMOS. Proposed Low Power Sense Amplifier Flip Flop with transition control detection (TCD-LPSAFF) and Ultra Low Energy Sense Amplifier Flip Flop (ULESAFF) give minimal power delay product (PDP) which is 35.7 × 10− 18 J and 29.6 × 10− 18 J respectively. Also, the effect of process variation has been analyzed at specified corners (FF, TT and SS) in the temperature range of -40∘C to 120 ∘C. The performance of all designs has been validated by functionality testing with variation in load cpacitance, diameter, number of tubes and pitch respectively.

A Sense Amplifier Based Modified Low Voltage Two Stage Flip-Flop with CNTFETs

The transformation from the event of enabling technology to the assembly of consumer-centric semiconductor products has empowered the designers to consider characteristics like robustness, compactness, efficiency, and scalability of the merchandise as implicit precursors. The Carbon Nanotube Field Effect Transistors (CNTFETs) are nowadays popular emerging technology. The paper proposes the sense amplifier-based two-stage flip-flop working within the sub-threshold region. the primary stage produces full swing conditional inputs for the latch stage. The proposed circuit has been designed using 16 CNTFETs. This circuit contains a significantly low clock load which reduces the power consumption. An improvement in the propagation delay and power delay product has also been achieved. Comparisons with other flip-flop designs manifest the robustness of the proposed circuit. The HSPICE software is used for simulating and verifying the theoretical results.

An energy‐efficient dynamic comparator in Carbon Nanotube Field Effect Transistor technology for successive approximation register ADC applications

In this paper, a latch-based energy-efficient dynamic comparator is presented in Carbon Nanotube Field Effect Transistor (CNTFET) technology. The proposed comparator consists of two main stages: pre-amplifier and latch. The latch stage is designed for the main purpose of low-power consumption and high-speed performances. The proposed speed-up technique for the latch structure controls the threshold voltage (Vth) of the cross-coupled inverters. So, the delay of the latch stage decreases and consequently, the overall delay of the comparator circuit is also reduced up to 19.4% while the maximum speed performance of the proposed comparator increases by 54% compared to the conventional double-tail dynamic comparator. Additionally, the use of the proposed distinctive structure for the tail transistors in the latch stage, leads to more than 11% reduction in the energy per conversion of the proposed circuit compared to the conventional double-tail dynamic comparator. To verify the circuit performances, the comparator circuit is simulated in HSPICE using 32 nm CNTFET Stanford model technology parameters. The simulation results show that the proposed comparator with the proposed speed-up approach can operate up to 14.2 GHz with a sensitivity of 30 μV at the supply voltage of 1 V, while consumes only 42.38 μW of power. Therefore, the proposed comparator can be used in high-resolution (up to 12 bit) and high-speed low-power analogue-to-digital converter applications. Moreover, the effects of the non-ideal fabrication process (including the pitch and the threshold voltage variations), supply voltage and temperature variations are investigated in this work. Monte-Carlo analysis shows that the standard deviation of the offset voltage is approximately 1.24 mV. Finally, the kickback noise of the proposed comparator is obtained as 80 μV, which shows the proper performance of the proposed comparator circuit in comparison with other reported designs.

Regenerative comparator with floating capacitor for energy‐harvesting applications

An energy-efficient regenerative comparator design is unveiled. A floating capacitor is utilized to protect the complete discharge of the preamplifier output nodes by NMOS input transistors. The introduced floating capacitor is flipped around the preamplifier to allow PMOS cross-couple transistor charge reutilization and elevate amplification gain at the integration phase. By increasing amplification gain, the input common mode voltage of the NMOS latch that is toggled within some delay is increased, too. Therefore, the latch stage is activated strongly, and regeneration delay is reduced. Simulation results corroborate that the proposed technique reduces power consumption and input-referred offset by more than 60% compared with results of similar previous works. Furthermore, the referred noise and delay are improved more than 30%.

A Low-Power High-Speed Sense-Amplifier-Based Flip-Flop in 55 nm MTCMOS

In this paper, a sense-amplifier-based flip-flop (SAFF) suitable for low-power high-speed operation is proposed. With the employment of a new sense-amplifier stage as well as a new single-ended latch stage, the power and delay of the flip-flop is greatly reduced. A conditional cut-off strategy is applied to the latch to achieve glitch-free and contention-free operation. Furthermore, the proposed SAFF can provide low voltage operation by adopting MTCMOS optimization. Post-layout simulation results based on a SMIC 55 nm MTCMOS show that the proposed SAFF achieves a 41.3% reduction in the CK-to-Q delay and a 36.99% reduction in power (25% input data toggle rate) compared with the conventional SAFF. Additionally, the delay and the power are smaller than those of the master-slave flip-flop (MSFF). The power-delay-product of the proposed SAFF shows 2.7× and 3.55× improvements compared with the conventional SAFF and MSFF, respectively. The area of the proposed flip-flop is 8.12 μm2 (5.8 μm × 1.4 μm), similar to that of the conventional SAFF. With the employment of MTCMOS optimization, the proposed SAFF could provide robust operation even at supply voltages as low as 0.4 V.

High-speed, low-power and low-offset fully differential double-tail dynamic comparator using charge sharing technique

To meet the demand for low-voltage/low-power and high speed analog-to-digital convertors, a new fully differential double-tail dynamic comparator is proposed. To reduce the power dissipation and speed up the comparison process, charge sharing technique has been used in the latch stage of the proposed dynamic comparator. In addition, differential pair and double-tail dynamic comparator topologies are combined to minimize the offset voltage. The proposed dynamic comparator has worst case delay of 0.219 ns, power dissipation of 156.3 μW and offset voltage of 0.184 mV with 1σ deviation of 7.65 mV. The proposed dynamic comparator has been simulated in 0.18 μm CMOS technology with supply voltages of ± 0.75 V using Cadence virtuoso analog design environment.

Design and analysis of ultra high-speed low-power double tail dynamic comparator using charge sharing scheme

In this paper, an ultra high speed dynamic comparator is presented. The PMOS pass transistors are used in the latch and pre-amplifier stage of the comparator. At the regeneration phase, the latch is activated faster with sufficient preamplification gain and very less power consumption. Meanwhile, a cross-coupled set up of NMOS transistors in latch stage enhances the gain and speed. Unlike the previous reported comparator, the proposed dynamic circuit avoids the extra power consumption as well as delay, and establishes the optimum offset and kickback noise. The benefits in delay and power are verified with the help of analytical expressions, meticulous Monte Carlo simulations and process corner analysis in CADENCE SPECTRE at 90 nm CMOS technology. The simulation results validate that the proposed structure provides the about 2.5 times better speed and minimizes the power consumption by 3 times in comparison to hybrid double tail dynamic comparator with only 0.348 fJ/conv. energy per conversion. Moreover, it provides 2.44 mV offset with optimum kickback noise and area.

Cross Coupled Differential High Speed Comparator

Power efficiency and high speed comparator is presented. ,n-MOS transistors are used to design preamplifier stage and the latch stage. Both stages are controlled by a special clock circuit. By using clock circuit we can achieve enough preamplification gain. At the evaluation phase, the latch is activated with a delay to obtain sufficient pre-amplification gain and avoid extra power consumption. At this phase transistors are cross coupled to increase the preamplifier gain and to lower the input voltage common mode of the latch is used to strongly activate the n-MOS transistors (on the latch input) and reduce the delay. This circuit is designed with n-MOS transistors due to its inherent superiority over the p-MOS transistor. The proposed cross coupled comparator reduces the power and delay compared to conventional CMOS comparators.

An Unbalanced Clock Based Dynamic Comparator: A High-Speed Low-Offset Design Approach for ADC Applications

Currently, dynamic comparator approach necessitates in high-speed and power efficient analog-to-digital converter applications due to its high latching speed and ultra-low power consumption. In this paper, a~novel dynamic comparator is proposed to reduce latch delay and offset. The comparator benefits from add-on cross-coupled transistors in latch structure and unbalanced clocks to enhance comparison speed and to lessen input offset voltage occurred due to mismatch in cross-coupled circuits in latch stage. The derivations for delay and input offset voltage are presented for proposed dynamic comparator with meticulous Monte-Carlo simulations. The results are verified by simulations in CADENCE SPECTRE at 1V supply voltage and 90nm CMOS technology. A~comparative analysis between the proposed dynamic comparator and the previous reported comparators has been presented. It is observed that the delay is reduced up to 46% and 6% as compared to conventional and two phase dynamic comparator, respectively. Moreover, the proposed design consumes 53.36muW power only. The Monte-Carlo simulation shows that the standard deviation of input offset voltage is 10.8~mV which is 12% and 77% of conventional and two phase dynamic comparator, respectively.

Low-power high-speed CMOS double tail dynamic comparator using self-biased amplification stage and novel latch stage

This paper presents a low voltage double-tail dynamic comparator (DTDC) for fast and power-efficient data conversion. The amplification stage of the proposed DTDC is designed using self-biasing technique, which helps to reduce external biasing requirement to bias bulk/gate of the transistors. The self-biasing technique controls threshold voltage (Vth) of the transistors either for fast switching (low-Vth) or for low power dissipation (high-Vth). The latch stage of the proposed DTDC is designed with novel dynamic CMOS inverters to improve the regeneration speed. The mathematical equations for delay and offset voltage are derived for the proposed DTDC and improvements are mentioned. The proposed DTDC is designed in CADENCE and simulated with SPECTRE using 45 nm CMOS process technology at the low power supply of 0.8 V to verify the outcomes. The simulation results reveal that the delay and power dissipation of the proposed DTDC are 166.29 pS and 2.3 µW respectively. The analysis of 1-sigma offset error is performed using Monte-Carlo simulation. Here, the mismatch and process variation are considered and the samples are generated randomly till 200 samples (runs). Additionally, the peak input voltage error due to kickback noise is 0.219 mV for a differential input voltage of 5 mV.

Design and Analysis of an Energy-Efficient High-Speed CMOS Double-Tail Dynamic Comparator with Reduced Kickback Noise Effect

This paper presents a novel high-speed and highly energy-efficient double-tail dynamic comparator. In order to achieve high speed, a hybrid design style is adopted for pre-amplifier stage and a new design is proposed for latch stage, which enhances the speed and reduces the effect of kickback noise. The latch stage delay and energy efficiency of the proposed design are optimized with respect to the width of each transistor. To verify the outcomes, the proposed comparator is simulated using 45[Formula: see text]nm and 180[Formula: see text]nm CMOS process. Monte Carlo simulation is also done for each parameter. The 45[Formula: see text]nm result shows that the comparator has the total delay as low as 104.3[Formula: see text]ps and consumes only 0.288[Formula: see text]fJ of energy per conversion from a 0.8[Formula: see text]V supply. The mean value of input voltage error due to kickback noise is found as 306[Formula: see text]nV.

Ultra‐low‐voltage low‐power dynamic comparator with forward body bias scheme for SAR ADC

An ultra-low-voltage two-stage dynamic comparator is proposed with a forward body bias (FBB) scheme for successive approximation register (SAR) analogue-to-digital converters (ADCs). The proposed FBB scheme for a preamplifier and latch stage reduces the delay time remarkably under a low supply voltage. At 0.4 V, the power consumption is 4.48 nW, and the delay can be decreased to 593.9 ns for ΔV in = 0.1 mV and f clk = 100 kHz. The RMS equivalent input-referred noise of the comparator is 0.136 mV. The total offset is 13.7 mV, and offset fluctuation is 0.183 mV with the proposed structure. Both the input-referred noise and offset fluctuation are <0.5 least-significant bit for a 10-bit SAR ADC at 0.4 V.

A Low-Power High-Speed Comparator for Precise Applications

A low-power comparator is presented. pMOS transistors are used at the input of the preamplifier of the comparator as well as the latch stage. Both stages are controlled by a special local clock generator. At the evaluation phase, the latch is activated with a delay to achieve enough preamplification gain and avoid excess power consumption. Meanwhile, small cross-coupled transistors increase the preamplifier gain and decrease the input common mode of the latch to strongly turn on the pMOS transistors (at the latch input) and reduce the delay. Unlike the conventional comparator, the proposed structure let us set the optimum delay for preamplification and avoid excess power consumption. The speed and the power benefits of the comparator were verified using solid analytical derivations, process–VDD–temperature corners, and Monte Carlo simulations along with silicon measurements in $0.18~\mu \text{m}$ . The tests confirm that the proposed circuit reduces the power consumption by 50% and provides 30% better comparison speed at the same offset and almost the same noise budgets. Moreover, the comparator provides a rail-to-rail input $V_{\text {cm}}$ range in $f_{\text {clk}} = 500$ MHz.

Wide‐input dynamic range 1 MHz clock ultra‐low supply flip‐flop

A new wide-input dynamic range flip-flop capable of operation at an ultra-low supply voltage of 0.16 V is presented. The proposed flip-flop named as capacitively boosted sense-amplifier flip-flop (CB-SAFF) utilises a capacitively boosted sense-amplifier master stage to sense the data signals and amplify them to a voltage higher than the supply and below the ground for driving the slave latch stage with improved strength. Using the same size of input/output transistors and load capacitance, the proposed CB-SAFF outperforms existing state-of-the-art sense-amplifier flip-flop designs at a low supply voltage operation from 0.16 to 0.6 V in terms of power delay product and clock to output propagation delay performance metrics. In addition, the proposed CB-SAFF can also sample low-swing data signals down to 0.2 V even at a 0.16 V supply voltage and 1 MHz clock frequency, thus making it highly suitable for applications that demand high speed and low power consumption such as for use in ultra-low voltage Internet of Things, wireless sensor nodes and smart motes.

A new high-speed low-power and low-offset dynamic comparator with a current-mode offset compensation technique

In this paper a new low-power high-speed offset-compensated dynamic latched comparator is presented. The proposed comparator uses a two-stage charge-steering preamplifier to achieve high pre-amplification voltage gain. Higher input voltage range of the latch stage significantly reduces the delay time of the latch and relaxes the need for high current in the regeneration process which ensures low-power structure. In addition, a new digitally controlled offset cancellation circuit based on the current-steering structure is used to reduce the offset of comparator. Offset voltage reduction in the startup time is the key advantage of the proposed calibration technique which does not require refreshing the offset cancellation process. Post-layout simulation results in 0.18µm standard TSMC CMOS process show that the designed comparator dissipates 135µW of power consumption from a 1.2V supply voltage and has the 1mV accuracy while operating at 1GHz clock frequency. The power and delay time of the proposed comparator are less than about 10% of the new state-of-the-art comparator. Furthermore, from the Monte-Carlo analysis, the standard deviation of the input referred offset voltage in typical process corner and temperature is obtained about 17.53/1.09mV before and after offset cancellation, respectively.

A 500 MHz low offset fully differential latched comparator

A fully differential latched comparator using a new offset cancellation technique is presented. The comparator consists of three stages: the input pre-amplifier, a positive feedback or latch stage and the offset cancellation circuitry. The effect of kick-back noise can be significantly reduced by using a pre-amplifier stage. Also, the offset and noise of the latch and offset cancellation stages are attenuated by the gain of the pre-amplifier when referred to the input. Latches regenerate faster than pre-amplifiers and provide a full swing digital output for the comparator. The last stage is the offset cancellation circuitry. The main advantage of the proposed offset cancellation technique is that it does not need to make any interrupt in normal operation of comparator to eliminate offset error. As a result, higher speeds for the comparator can be achieved. Moreover, the power consumption of the proposed offset cancellation circuitry is negligible compared to the overall power consumption. In order to evaluate the performance of the comparator, simulations are performed in a 0.18 μm standard CMOS technology. Simulation results show that the offset values of the pre-amplifier and latch stages are significantly eliminated by this cancellation technique and only about 450 μV offset voltage will be referred to the input due to offset error of the offset cancellation circuitry. The proposed comparator operates at 500 MHz clock frequency and dissipates 373 μW from a 1.8 supply. Also, it has a propagation delay of 138 ps and kick-back noise of 0.54 mV.

High Temperature Bipolar Master-Slave Comparator and Frequency Divider in 4H-SiC Technology

This paper demonstrates a fully integrated master-slave emitter-coupled logic (ECL) comparator and a frequency divider implemented in 4H-SiC bipolar technology. The comparator consists of two latch stages, two level shifters and an output buffer stage. The circuits have been tested up to 500 °C. The single ended output swing of the comparator is -7.73 V at 25 °C and -7.63 V at 500 °C with a -15 V supply voltage. The comparator consumes 585 mW at 25 °C. The frequency divider consisting of two latches shows a relatively constant output voltage swing over the wide temperature range. The output voltage swing is 7.62 V at 25 °C and 7.32 V at 500 °C.