Abstract
In this paper, a sense-amplifier-based flip-flop (SAFF) suitable for low-power high-speed operation is proposed. With the employment of a new sense-amplifier stage as well as a new single-ended latch stage, the power and delay of the flip-flop is greatly reduced. A conditional cut-off strategy is applied to the latch to achieve glitch-free and contention-free operation. Furthermore, the proposed SAFF can provide low voltage operation by adopting MTCMOS optimization. Post-layout simulation results based on a SMIC 55 nm MTCMOS show that the proposed SAFF achieves a 41.3% reduction in the CK-to-Q delay and a 36.99% reduction in power (25% input data toggle rate) compared with the conventional SAFF. Additionally, the delay and the power are smaller than those of the master-slave flip-flop (MSFF). The power-delay-product of the proposed SAFF shows 2.7× and 3.55× improvements compared with the conventional SAFF and MSFF, respectively. The area of the proposed flip-flop is 8.12 μm2 (5.8 μm × 1.4 μm), similar to that of the conventional SAFF. With the employment of MTCMOS optimization, the proposed SAFF could provide robust operation even at supply voltages as low as 0.4 V.
Highlights
High speed and low power is the theme of digital circuits
In order to verify the validity of the proposed sense-amplifier-based flip-flop (SAFF), the master–slave flip-flop (MSFF), the conventional SAFF, Nikolic’s SAFF, Lin’s SAFF and
Hspice with the same settings is adopted to perform all post-layout simulations for comparisons. The performance comparisons such as of the area, power consumption, CK-to-Q delay, setup time and hold time of the various flip-flops are described in detail below
Summary
High speed and low power is the theme of digital circuits. As basic storage elements, the delay and power of the flip-flops directly determines the performance and power of digital systems. The sense-amplifier-based flip-flop (SAFF), first appearing in [7], is another fast flip-flop with a near-zero or negative setup time. With a near-zero or negative setup time and a reduced hold time, the SAFF is a good candidate to substitute MSFF in the standard cell library for high-speed design. Even though these features are attractive, the SAFF has several problems. The pre-charge operation of the SAFF will increase power consumption, and a fast latch structure is needed to reduce the CK-to-Q delay.
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