Evaluation of Sense Amplifier Flip-Flop with Completion Detection Signal

Abstract

Sense amplifier is a part of read circuitry used to read data from memory. It amplifies the low voltage signals to high logic level signal. It has wide range of applications such as in memory storage, level shifter and bus driver. This paper explains the design of Sense Amplifier based flip flop (SAFF) with control signal as Transition Completion Detection (TCD). The flip flop (FF) is designed in gpdk180nm technology and simulated using Cadence tool. Performance analysis of Conventional SAFF, Power PC master slave flip flop and SAFF with control signal TCD are compared in terms of delay, power and power delay product. Power for different value of voltage is compared for designed FF. Simulation results show that, 6% reduction of power for Sense amplifier FF with control signal TCD compared to Power PC Master slave FF at 1 volt supply voltage. Compared to Conventional SAFF, designed SAFF with control signal TCD reduces clock to Q delay about 4.7%. To analyze the working operation of SAFF with control signal TCD, a new circuit proposed and is designed using 2:1 multiplexer. Simulation result shows that, power and clock to Q delay of designed circuit are in the order of 26.87 µwatt and 30.23 nsec respectively.