Large Junction Area Research Articles

Thin-film photodiode based on novel SiC/MoS2 composite by RF-sputtering for fast response photodetection

A Schottky -photodiode and pn-photodiode were fabricated based on a SiC/MoS2 composite semiconductor material using a physical vapour deposition (PVD) method. The surface topology and structural features of the nanostructured SiC/MoS2 thin films were investigated using scanning electron microscope (SEM), Fourier Transform Infrared spectroscopy (FTIR), and grazing incidence X-Ray diffraction (GIXRD) analysis. The two-dimensional nature of these materials enables easiness integration for vertical device design with novel properties. The performance parameters of the fabricated devices were characterized. The electrical performance of the fabricated SiC/MoS2 Schottky and pn photodiodes were investigated according to their current-voltage (I–V) characteristics within a bias voltage range from −4 to 4 V. Here, we report highly efficient photocurrent generation from vertical SiC/MoS2 composite device fabricated using asymmetric metal contacts, exhibiting an external quantum efficiency (EQE) of up to 14.68% for pn -photodiode and 6.68% for Schottky -photodiode. Evaluated to in-plane MoS2 devices, the vertical design of these devices has a much larger junction area which is essential for achieving highly efficient photovoltaic devices. As well as spectral responsivity of 28.25 mA/W and 63.22 mA/W for Schottky and pn-photodiodes respectively also, response time of 1 ms for Schottky-photodiode and 977.5 μs for pn-photodiode were measured and discussed.

Constructing 2D/2D La2Ce2O7/g-C3N4 S-scheme heterojunction for markedly enhanced interfacial charge separation and photocatalytic activity under visible light irradiation

It is an effective strategy to improve photocatalytic degradation performance by constructing step scheme (S-scheme) heterojunction photocatalysts with superior photo-redox capacity and high charge transfer efficiency. In this study, a series of two-dimensional/two-dimensional (2D/2D) La2Ce2O7/g-C3N4 (LCO/CN) S-scheme heterojunction photocatalysts were synthesized via in-situ solid-phase sintering by regulating the mass ratio of raw materials. The large junction area between La2Ce2O7 nanosheets and ultra-thin graphitic carbon nitride (g-C3N4) endows the composite with significantly enhanced separation and transfer efficiency of photogenerated carriers within a satisfactory light response region. The LCO/CN-2 composite not only shows the highest photocatalytic activity with a reaction rate constant of 0.02701 min−1 to degrade Rhodamine B (RhB) under visible light irradiation for 90 min but also demonstrates stable reusability after four runs. Moreover, based on the Mott-Schottky calculations, radical trapping experiments, and ESR analysis,·O2- and·OH are identified as the main active species, and an S-scheme charge transfer mechanism is suggested to explain the enhanced photocatalytic activity. This work inspires the application of fluorite-type photocatalysts to wastewater purification and environmental restoration.

Mixed-dimensional CsPbBr3@ZnO heterostructures for high-performance p-n diodes and photodetectors

Mixed one-dimensional (1D) and three-dimensional (3D) heterostructures, with synergistic advantages of different dimensionalities, have shown unique optical properties due to their large junction areas and high absorption cross-sections, which may also bring superior electrical and optoelectronic performances. However, due to the challenge in designing and constructing a proper 1D-3D p-n junction, their electronic properties and potential application are still unclear. Here, a type of 1D-3D ZnO/CsPbBr3 p-n junction is constructed by liquid-phase growth of crystalline CsPbBr3 microplates on ZnO nanowires, which exhibit excellent properties of p-n diode and serve as high-performance rectifier and photodetector. As a rectifier, it shows characteristics of ambipolar transfer and its rectification ratio reaches up to 106. As a photodetector, it covers light from ultraviolet to visible light. High photoelectric switching ratio (107), responsivity (3.5 × 103 A/W), detectivity (6.6 × 1013 Jones) and external quantum efficiency (1.7 × 106%) are obtained under 254 nm light illumination. Meanwhile, the switching ratio, responsivity, detectivity and external quantum efficiency are 103, 41.5 A/W, 4.96 × 1012 Jones and 1.086 × 103%, respectively, under 473 nm laser illumination. The decay length of photo-generated carriers in ZnO/CsPbBr3 heterojunction is demonstrated longer than that in original CsPbBr3 crystal, which is further controlled by adjusting the potential barriers between the CsPbBr3 and ZnO with a tunable external electric field.

Interfacial ZnS passivation for improvement of transparent ZnO/CuI diode characteristics

To fabricate a n-ZnO/p-CuI heterojunction diode with a high rectification ratio at a large junction area, γ-CuI film was spin-coated on ZnO. Since the n-ZnO/p-CuI diode showed a rectification ratio as small as 2.38 × 102, the ZnS interfacial layer was prepared by successive ionic layer adsorption and reaction. By placing a ZnS layer between the n-ZnO/p-CuI, the rectification ratio from the diode increased to 1.71 × 107 at a junction area of 1 cm2. Modification of the valence band offset and the conduction band offset of the n-ZnO/p-CuI junction in the presence of the interfacial ZnS layer may facilitate carrier transport between ZnO and CuI. In addition, it was confirmed that two types of defects (oxygen vacancy and unpaired electron trapped on an oxygen vacancy) were reduced by insertion of an interfacial ZnS layer. A significant improvement in the rectification ratio resulted from the large decrease in the reverse current in the ZnO/CuI diode by a reduced amount of oxygen vacancies. Therefore, the improvement of band alignment with the decrease in the interfacial defects by the introduction of wide bandgap ZnS passivation layer enhanced the electrical characteristics of ZnO/CuI diode.

Representation of an engineered double-step structure SOI-TFET with linear doped channel for electrical performance improvement: a 2D numerical simulation study

In this paper, a novel double-step (DS) structure tunnel field-effect transistor with a linear doping profile channel (DSS-LDC-TFET) is presented. The use of a step-shaped structure near the source/channel interface leads to the large tunneling junction area because the band-to-band tunneling of the carriers occurs perpendicularly along the conducting path in the channel. The step-shape of the channel/drain interface reduces the electric field distribution near the drain junction which helps to suppress the ambipolar behavior. Further, the DS structure of the body suppresses the ambipolar conduction due to increasing the effective length of channel area along the device. Therefore, the height of the steps in the proposed structure plays an important role in the device characteristics. The doping profile in the channel region is considered to be linear. The maximum value of the doping concentration is at the source side and linearly decreases to its minimum value along the x-axis. Numerical simulation results show that using the linear doping distribution at the channel improves device behavior through reducing the tunneling barrier width at the source/channel interface. The optimum length for the linear-doped part of the channel is selected to maximize the on-state current without degrading much the off-state current. Finally, the comparative study between DSS-LDC-TFET with the conventional silicon-on-insulator tunnel field-effect transistor is presented.

Binary-Structured Si Surface Modification by an Alkaline Treatment: Application to Poly(3,4-Ethylenedioxythiophene)-Poly(Styrene Sulfonate)/Silicon Heterojunction Solar Cells

In recent years, silicon-organic hybrid solar cells have attracted tremendous research attention owing to their low production cost and high performance. In the present work, tapered silicon nanowires (TSiNWs) were synthesized on random micro-pyramids (RM pyramids). On this binary structure, a poly(3,4-ethylenedioxythiophene)-poly(styrene sulfonate) (PEDOT:PSS) polymer was spin-coated. The tapering of SiNWs was performed by immersing the samples in NaOH solution. It was found that the tapering time affects significantly the reflectivity, the minority carriers lifetime and the coverage rate of Si surface by the PEDOT:PSS film. Indeed, an optimal tapering time of 6 s was determined. This time was sufficient to good incident light trapping and to reduce the surface defects. This simple and low-cost surface structuring technique holds high potential for improving the performance of hybrid solar cells with large junction area.

Source-all-around tunnel field-effect transistor (SAA-TFET): proposal and design

In this paper, a new source-all-around tunnel field-effect transistor (SAA-TFET) is proposed and investigated by using TCAD simulation. The tunneling junction in the SAA-TFET is divided laterally and vertically with respect to the channel direction which provides a relatively large tunneling junction area. An n+ pocket design is also introduced around the source to enhance tunneling rates and improve the device characteristics. In addition, the gate and n+ pocket region also overlap in the vertical and the lateral directions resulting in an enhanced electric field and, in turn, the ON-state current of the SAA-TFET is highly increased compared with the conventional TFET. Promising results in terms of DC (ION, IOFF, ON/OFF current ratio and SS) and analog (cutoff frequency) performance are obtained for low (VDD = 0.5 V) and high (VDD = 1 V) supply voltages.

Improved Performance of Silicon Nanowire-Based Solar Cells with Diallyl Disulfide Passivation

Silicon nanowires (SiNWs) have attracted increasing attention for their enhanced light harvesting and large junction area of photovoltaic devices compared to planar silicon wafers. However, high su...

Growth and Fabrication of High‐Quality Single Nanowire Devices with Radial p‐i‐n Junctions

Nanowires (NWs) with radial p-i-n junction have advantages, such as large junction area and small influence from the surface states, which can lead to highly efficient material use and good device quantum efficiency. However, it is difficult to make high-quality core-shell NW devices, especially single NW devices. Here, the key factors during the growth and fabrication process that influence the quality of single core-shell p-i-n NW devices are studied using GaAs(P) NW photovoltaics as an example. By p-doping and annealing, good ohmic contact is achieved on NWs with a diameter as small as 50-60 nm. Single NW photovoltaics are subsequently developed and a record fill factor of 80.5% is shown. These results bring valuable information for making single NW devices, which can further benefit the development of high-density integration circuits.

Organic Photovoltaic Switches Using DBP/C60 Cells and Blue Light to Trigger Logic and Amplifier Electronics

Apart from ordinary solar cell applications, we have attempted different approaches of device applications. We have fabricated two types of organic photovoltaic (OPV) cells with DBP/C60 heterojunction and measured their spectral photo responses when they are in planar heterojunction (PHJ) and bulk heterojunction (BHJ) type. According to our results, blue light exhibits spectrally outstanding PV effects and the PHJ device showed higher open circuit voltage (VOC) along with ten times faster switching photo-dynamics than those performances of BHJ device, although the mixture type BHJ diode appears much superior to PHJ diode in all spectral ranges of quantum efficiency. Large junction area of mixture type OPV diode is certainly an advantage in photocurrent generation and quantum efficiency, but is regarded as a disadvantage for dynamic PV switching and VOC value because complex route and high density interface traps are unavoidable in BHJ structure. Selecting the blue light illumination on DBP/C60 PHJ diode, we achieve most efficient PV switching and PV gating in logic and amplifier circuits, respectively. Conclusively, bilayer OPV device has its own advantage over mixture type device in dynamic PV switching, and it promises future electronics by exploiting the dynamic harvest of light energy. Figure 1

Photovoltaic cell electrical heating system for removing snow on panel including verification.

Small photovoltaic plants in private ownership are typically rated at 5kW (peak). The panels are mounted on roofs at a decline angle of 20° to 45°. In winter time, a dense layer of snow at a width of e.g., 10cm keeps off solar radiation from the photovoltaic cells for weeks under continental climate conditions. Practically, no energy is produced over the time of snow coverage. Only until outside air temperature has risen high enough for a rather long-time interval to allow partial melting of snow; the snow layer rushes down in an avalanche. Following this proposal, snow removal can be arranged electrically at an extremely positive energy balance in a fast way. A photovoltaic cell is a large junction area diode inside with a threshold voltage of about 0.6 to 0.7V (depending on temperature). This forward voltage drop created by an externally driven current through the modules can be efficiently used to provide well-distributed heat dissipation at the cell and further on at the glass surface of the whole panel. The adhesion of snow on glass is widely reduced through this heating in case a thin water film can be produced by this external short time heating. Laboratory experiments provided a temperature increase through rated panel current of more than 10°C within about 10min. This heating can initiate the avalanche for snow removal on intention as described before provided the clamping effect on snow at the edge of the panel frame is overcome by an additional heating foil. Basics of internal cell heat production, heating thermal effects in time course, thermographic measurements on temperature distribution, power circuit opportunities including battery storage elements and snow-removal under practical conditions are described.

High performance broadband photodetector based on MoS2/porous silicon heterojunction

A high speed efficient broadband photodetector based on a vertical n-MoS2/p-porous silicon heterostructure has been demonstrated. Large area MoS2 on electrochemical etched porous silicon was grown by sulphurization of a sputtered MoO3 thin film. A maximum responsivity of 9 A/W (550–850 nm) with a very high detectivity of ∼1014 Jones is observed. Transient measurements show a fast response time of ∼9 μs and is competent to work at high frequencies (∼50 kHz). The enhanced photodetection performance of the heterojunction made on porous silicon over that made on planar silicon is explained in terms of higher interfacial barrier height, superior light trapping property, and larger junction area in the MoS2/porous silicon junction.

A Novel PNPN-Like Z-Shaped Tunnel Field- Effect Transistor With Improved Ambipolar Behavior and RF Performance

To suppress the ambipolar behavior and improve RF performance in tunnel field-effect transistors (TFETs), a Z-shaped (ZS)-TFET is proposed. The proposed ZS-TFET is more scalable than other vertical band-to-band-based TFETs and provides higher ON-state current ( ${I} _{ {\mathrm{\scriptscriptstyle ON}}}$ ), larger ON/OFF current ratio ( ${I} _{ {\mathrm{\scriptscriptstyle ON}}}/{I} _{ {\mathrm{\scriptscriptstyle OFF}}}$ ) and lower subthreshold swing compared to conventional TFETs. These advantages stem from the tunneling junction in the ZS-TFET being perpendicular to the channel direction, which facilitates the formation of a relatively large tunneling junction area. The ZS body makes use of both vertical and horizontal fields while suppressing the lateral parasitic tunneling current. In addition, by using a ZS gate in the proposed device, the energy band diagram near the source is modulated to create an N+ source pocket which creates a downward band bending of the potential, similar to PNPN-like structures. Finally, the proposed structure significantly improves the analog/RF figure-of-merit.

Highly efficient, high speed vertical photodiodes based on few-layer MoS2

Layered transition metal dichalcogenides, such as MoS2, have recently emerged as a promising material system for electronic and optoelectronic applications. The two-dimensional nature of these materials enables facile integration for vertical device design with novel properties. Here, we report highly efficient photocurrent generation from vertical MoS2 devices fabricated using asymmetric metal contacts, exhibiting an external quantum efficiency of up to 7%. Compared to in-plane MoS2 devices, the vertical design of these devices has a much larger junction area, which is essential for achieving highly efficient photovoltaic devices. Photocurrent and photovoltage spectra are measured over the photon energy range from 1.25 to 2.5 eV, covering both the 1.8 eV direct K-point optical transition and the 1.3 eV Σ-point indirect transition in MoS2. Photocurrent peaks corresponding to both direct and indirect transitions are observed in the photocurrent spectra and exhibit different photovoltage–current characteristics. Compared to previous in-plane devices, a substantially shorter photoresponse time of 7.3 μs is achieved due to fast carrier sweeping in the vertical devices, which exhibit a −3 dB cutoff frequency of 48 kHz.

Tunnel Field-Effect Transistor With an L-Shaped Gate

In this letter, a new L-shaped gate tunnel field-effect transistor (LG-TFET) is proposed and investigated by Silvaco Atlas simulation. The tunneling junction in the LG-TFET is perpendicular to the channel direction that facilitates the implementation of a relatively large tunneling junction area. The channel is U-shaped that makes the channel mainly distribute in the vertical direction, reducing the device area. The n+ pocket design is also introduced between the source and the intrinsic regions to improve the device characteristic. In addition, the gate and n+ pocket region overlap both in the vertical and the lateral directions resulting in an enhanced electric field, and the ON-state current of the LG-TFET is increased up to $\sim 50$ % compared with the previous L-shaped channel TFET. The minimum subthreshold swing of the LG-TFET is 38.5 mV/decade at 0.2 V gate-to-source voltage. By using the L-shaped gate, U-shaped channel, and the insertion of n+ pocket, the overall performance of the LG-TFET is optimized.

High-sensitivity and self-driven photodetectors based on Ge–CdS core–shell heterojunction nanowires via atomic layer deposition

Core–shell p–n heterojunction nanowires (NWs) hold great promise for optoelectronic applications due to the large effective junction area and minimized carrier recombination. However, the rational design and synthesis of core–shell heterojunction NWs are hindered by the complex fabrication process and the potential damage to core NWs during shell deposition. Herein, we demonstrated the fabrication of Ge–CdS core–shell heterojunction NWs via a facile atomic layer deposition (ALD) technique. The ALD technique allowed the conformal deposition of polycrystalline CdS shells on single-crystalline Ge NWs with high uniformity and controllable thickness. The heterojunction NWs exhibited excellent diode characteristics, with a pronounced photoresponse under light illumination. Significantly, owing to the existence of a built-in electric field, the heterojunctions could serve as self-driven photodetectors, with a high photosensitivity of 18000%, which is remarkably much better than previous reports on Ge NW photodetectors. The complementary bandgaps of Ge and CdS also ensured that the device had a capability for broadband detection from visible to infrared light. This study represents an important advance in fabricating core–shell heterojunction NWs for high-performance optoelectronic applications.

Role of Junction Geometry in Determining the Rectification Performance of Nanostructured TiO<sub>2</sub>-Based p-n Junctions

This paper reports on the influence of junction geometry on the determination of the rectification performance of nanostructured titanium dioxide (TiO2)-based p-n homojunctions. Two types of p-n junction devices with different junction area/geometry were fabricated. Sol–gel grown undoped TiO2 nanoparticle layer was employed as the p-type side in both the cases. Electrochemically grown TiO2 nanotube array was used as the n-type side in one junction, while thermally grown n-TiO2 thin film was used in another. It was found that, due to unique advantage of excessively large junction area, p-TiO2/n-TiO2 nanotube device offered a dramatically improved ideality factor (4) and a rectification factor (1093) compared with its p-TiO2/n-TiO2 (thermally grown) counterpart (17 and 34, respectively). The 2-D distribution probability of the depletion region in the case of the first device was empirically correlated with the experimental findings and was supported by the corresponding $C$ – $V$ measurement results.

Improved Performance in Mirror-Assisted Back-Contact CMOS Photovoltaic Devices

Improved performance in CMOS interdigitated back-contact photovoltaic devices (IBC-PVs) is demonstrated by utilizing interdigitated junctions and a back metal reflector to simultaneously achieve large total junction area, uniform series resistance, and high optical back reflection. Enhanced ultimate efficiency of 20.33% is experimentally obtained from a 35-μm thick CMOS IBC-PV with a junction period of 7.2 μm under 980-nm illumination. Since the proposed IBC-PVs are implemented by standard bulk CMOS process, it can be easily integrated with other microelectronics to realize a self-power system for a variety of applications.

Hybrid Fabrication of Highly Rectifying <inline-formula> <tex-math notation="LaTeX">$p$ </tex-math></inline-formula>-<inline-formula> <tex-math notation="LaTeX">$n$ </tex-math></inline-formula> Homojunction Based on Nanostructured TiO<sub>2</sub>

Present report concerns fabrication of nanostructured TiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -based p-n homojunction, by the hybrid technique involving deposition of sol-gel grown not intentionally doped p-type TiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> nanoparticle layer over the electrochemically grown aligned, n-type TiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> nanotube array. The Au/p-TiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /n-TiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> nanotube/Ti device was found to offer the ideality factor and the cut-in voltage of ~4 and ~1.2 V, respectively, in the temperature range of 30°C-80°C. The structural advantages of TiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> nanotubes, owing to the large junction area, eventually offered attractive rectifying behavior (~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> orders) of the fabricated junction.

Fabrication of silicon nanowire/poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate)-graphene oxide hybrid solar cells

Silicon nanowire (SiNW)/Poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS) Schottky junctions have shown great promise as high efficiency, cost effective solar cells. Here, hybrid SiNWs/PEDOT:PSS blended graphene oxide (GO) solar cells are prepared and investigated. The SiNWs/PEDOT:PSS blended GO cells show enhanced light trapping and a large junction area when compared to pure PEDOT:PSS structures. SiNWs combined with GO solar cells show energy conversion efficiencies of up to 9.57% under the AM 1.5G condition, opening the possibility of using semiconductor/graphene oxide in photovoltaic applications.