Large Wafers Research Articles

Double-Sided Polishing Simulation Based on the Gap Theory - Theory of Pressure Distribution Analysis and Conditions for High Flatness

The double sided polishing technique is often applied to achieve high total thickness variance (TTV) of large silicon wafers that are employed to manufacture integrated circuit (IC) cards and smartphones. However, the theoretical analysis of high TTV is not sufficiently studied for the double sided polishing. Whereas, a polishing simulation for single sided polishing based on the gap theory was already developed. This simulation results were compared to the experimental results and indicate good behavior characteristics. This study presents a description of the theory for analyzing pressure distribution for double sided polishing and the simulation results of the surface generation process. It was demonstrated that the average of total running distance is nearly equal for the upper and the lower plates. Improved flatness is obtained when the rotation speed differences of the upper and lower plate rotations for the carrier revolution are equal. Furthermore, it was shown that TTV of less than 0.04 μm with a flatness of less than 0.05 μm may be attained when the cone upper plate with the optimum slope and the flat lower plate are employed with lower carrier rotation.

From Wafers to Bits and Back again: Using Deep Learning to Accelerate the Development and Characterization of SiC

A non-destructive, fast and accurate extended defect counting method on large diameter SiC wafers is presented. Photoluminescence (PL) signals from extended defects on 4H-SiC substrates were correlated to the specific etch features of Basal Plane Dislocations (BPDs), Threading Screw Dislocations (TSDs), and Threading Edge Dislocations (TED). For our non-destructive technique (NDT), automated defect detection was developed using modern deep convolutional neural networks (DCNN). To train a robust network, we used our large volume data set from our selective etch method of 4H-SiC substrates, already established based on definitive correlations to Synchrotron X-Ray Topography (SXRT) [1]. The defect locations, classifications and counts determined by our DCNN correlate with the subsequently etch-delineated features and counts. Once our network is sufficiently trained we will no longer need destructive methods to characterize extended defects in 4H-SiC substrates.

Non-Plasma Dry Etcher Design for 200 mm-Diameter Silicon Carbide Wafer

For improving the productivity of the semiconductor silicon carbide power devices, a very large diameter wafer process was studied, particularly for the non-plasma wafer etching using the chlorine trifluoride gas. Taking into account the motion of heavy gas, such as the chlorine trifluoride gas having the large molecular weight, the transport phenomena in the etching reactor were evaluated and designed using the computational fluid dynamics. The simple gas distributor design for a 200-mm-diameter wafer was evaluated in detail in order to uniformly spread the etchant gas over the wide wafer surface.

Lattice performance during initial steps of the Smart-Cut™ process in semiconducting diamond: A STEM study

An alternative route for the development of diamond-based technologies is the Smart-Cut process. Such a process could make possible the combination of diamond and silicon technologies, as well as building alternative structures or manufacturing large diamond wafers. However, crystalline quality and implantation-related damages may alter the electronic properties of the diamond wafer. In fact, this is a critical bottleneck that needs to be analysed in order to develop a reliable diamond/Smart-Cut based technology. In this contribution, we present STEM-based experiments used to evaluate various key parameters such as the sharpness of the transition regions, the behaviour of the implanted region and diamond lattice performance in Smart-Cut processes. Indeed, an outstanding sp2/sp3 relation close to ideality (it is, that of undamaged diamond) is evidenced in the diamond-transfer region.

GaN and Ga2O3-based wide bandgap semiconductor devices for emerging nanoelectronics

III-nitride wide bandgap semiconductors such as alloys of (Al, Ga, In) N play a vital role in high frequency, power electronics, and opto-nanoelectronics applications. Apart from this recently, wide bandgap semiconductor, β-Ga2O3 has attracted the attention of worldwide researchers as an alternative of GaN substrates due to its low-cost processing and wide availability of large scale wafers. Due to its suitable material properties, β-Ga2O3 can also be used for high frequency and high power electronics applications. In this paper the quantum transport in AlN/β-Ga2O3 based high electron mobility transistor (HEMT) along with the compact model development of GaN-based metal oxide semiconductor (MOS)-HEMT is presented for high frequency and high power electronics. Finally, the modeling and simulations of InGaN based nanowire is developed for solar photovoltaics and opto-nanoelectronics applications.

An extended Stoney's formula including nonlinear deformation for large size wafer of multilayers with arbitrary thicknesses

Applying the principle of minimum potential energy in an invariant plane reference frame, we obtain a concise curvature-strain equation for large size thick multilayered wafer, which incorporates strain due to nonlinear deformation. This equation manifests itself as Stoney's or other famous formulas for specific cases, and clarifies their relations and physical origins. We find nonlinear deformation greatly suppresses wafer bending and verify this effect experimentally in 2–4 in. GaN/sapphire systems. Such mechanical analysis provides a foundation of curvature control which is crucial in wafer fabrication for electronics and photonics.

Large and Dense Organic-Inorganic Hybrid Perovskite CH3NH3PbI3 Wafer Fabricated by One-Step Reactive Direct Wafer Production with High X-ray Sensitivity.

Lead halide perovskites with good optoelectronic properties and high attenuation of high-energy radiation are great candidates for X-ray radiation detectors. Large area, dense, and thick films or wafers are a prerequisite for these applications. In this paper, a one-step heat-assisted high-pressure press method is developed to directly prepare a large (the largest has a diameter of 80 mm) and thickness- and shape-controlled phase-pure organic-inorganic hybrid CH3NH3PbI3 wafer of densely packed large microcrystals from raw powder materials. Meanwhile, this method uses no solvent to achieve essentially 100% material utilization. The obtained wafers show good ambipolar carrier mobilities of ∼20 cm2 V-1 s-1 and a μτ product as high as 3.84 × 10-4 cm2 V-1. Under an X-ray source using an acceleration voltage of 40 kV, the perovskite wafer-based X-ray detector shows an X-ray sensitivity as large as 1.22 × 105 μC Gyair-1 cm-2 under a 10 V bias, the highest reported for any perovskite material. The method provides a convenient strategy for producing large perovskite wafers with good optoelectronic properties, which will facilitate the development of large perovskite devices.

Laser-based Thickness Control in a Double-Side Polishing System for Silicon Wafers.

Thickness control is a critical process of automated polishing of large and thin Si wafers in the semiconductor industry. In this paper, an elaborate double-side polishing (DSP) system is demonstrated, which has a polishing unit with feedback control of wafer thickness based on the scan data of a laser probe. Firstly, the mechanical structure, as well as the signal transmission and control of the DSP system, are discussed, in which the thickness feedback control is emphasized. Then, the precise positioning of the laser probe is explored to obtain the continuous and valid scan data of the wafer thickness. After that, a B-spline model is applied for the characterization of the wafer thickness function to provide the thickness control system with credible thickness deviation information. Finally, experiments of wafer-thickness evaluation and control are conducted on the presented DSP system. With the advisable number of control points in B-spline fitting, the thickness variation can be effectively controlled in wafer polishing with the DSP system, according to the experimental results of curve fitting and the statistical analysis of the experimental data.

Manufacturing processes for fabrication of flip-chip micro-bumps used in microelectronic packaging: An overview

Electronic packaging is the methodology for connecting and interfacing the chip technology with a system and the physical world. The objective of packaging is to ensure that the devices and interconnections are packaged efficiently and reliably. Chip–package interconnection technologies currently used in the semiconductor industry include wire bonding, tape automated bonding and flip-chip solder bump connection. Among these interconnection techniques, the flip-chip bumping technology is commonly used in advanced electronic packages since this interconnection is an area array configuration so that the entire surface of the chip can be covered with bumps for the highest possible input/output (I/O) counts. The present article reviews the manufacturing processes for the fabrication of flip-chip bumps for chip–package interconnection. Various solder bumping technologies used in high-volume production include evaporation, solder paste screening and electroplating. Evaporation process produces highly reliable bumps, but it is extremely expensive and is limited to lead or lead-rich solders. Solder paste screening is cost-effective, but issues related to excessive void formation limits the process to low-end products. On the other hand, electrochemical fabrication of flip-chip bumps is an extremely selective and efficient process, which is extendible to finer pitch, larger wafers and a variety of solder compositions, including lead-free alloys. Electrochemically fabricated copper pillar bumps offer fine pitch capabilities with excellent electromigration performance. Due to these virtues, the copper pillar bumping technology is emerging as a lead-free bumping technology option for high-performance electronic packaging.

A study on the nucleation and MPCVD growth of thin, dense, and contiguous nanocrystalline diamond films on bare and Si3N4-coated N-polar GaN

We report upon the microwave plasma chemical vapor deposition (MPCVD) growth of polycrystalline diamond on varying crystallographic orientations of GaN (Ga-polar and N-polar), as well as on Si3N4-coated N-polar GaN, as applied to top-side heat spreading layers for III-N-based high electron mobility transistors. Integration of diamond with GaN in this configuration is subject to differing process constraints from previous research focusing on backside heat sinks. A critical requirement is to prevent hydrogen-related etching of the III-N surface in the H+ plasma ambient, as well as to avoid plasma damage to the GaN crystal or HEMT channel region near the surface. Thus we developed the seeding and MPCVD techniques under a low power density plasma with low sample temperatures during deposition. We systematically investigated samples seeded via polymer-assisted dip seeding in a nanoparticle suspension, which were then subjected to MPCVD growth under identical conditions. We evaluated the quality of the films via scanning electron microscopy and Raman spectroscopy to understand the relationship between grain size, interface abruptness, propensity for surface etching, as well as film uniformity. Finally, we were able to identify a process window for both N-polar GaN and Si3N4-coated N-polar GaN which yields thin, fully coalesced, nanocrystalline diamond films with an abrupt interface to the underlying substrate. These diamond films exhibit microscopic uniformity in crystal grain size, and macroscopic uniformity in thickness and interface abruptness via a process which is scalable to large wafer sizes.

Fully epitaxial magnetic tunnel junction on a silicon wafer

We developed a fully epitaxial magnetic tunnel junction on an 8″ silicon wafer by using a mass-production sputtering apparatus and achieved a high magnetoresistance ratio exceeding 240% at room temperature. One of the key factors in this achievement is the use of a B2-type Ni-Al seed layer on the wafer as a (001)-oriented and an atomically smooth template. Another is the insertion of a thin Al layer prior to MgO sputtering as protection from plasma damage, resulting in the formation of a spinel-type single-crystal Mg-Al-O tunnel barrier after in situ annealing. This epitaxial technology for transition metals on large wafers will lead to advanced practical spintronics devices incorporating high-performance single-crystalline materials such as chemical-ordered alloys and tunnel barriers.

24.58% total area efficiency of screen-printed, large area industrial silicon solar cells with the tunnel oxide passivated contacts (i-TOPCon) design

We demonstrate an “industrial tunnel oxide passivated contacts” (i-TOPCon) silicon solar cell on large area n-type silicon wafers (156.75 mm × 156.75 mm). This cell has a boron diffused front emitter, a tunnel-SiOx/n+-poly-Si/SiNx:H structure at the rear side, and screen-printed electrodes on both sides. The passivation of the tunnel-SiOx/n+-poly-Si/SiNx:H structure on silicon wafers is investigated. The saturation currents Jo of this structure on polished and textured silicon surfaces are 1.3 and 3.7 fA/cm2, respectively. After printing the Ag contacts, the Jo of this structure increases to 50.7 fA/cm2 on textured silicon surfaces, which is still manageably low for metal contacts. This structure was applied to i-TOPCon solar cells, resulting in a median efficiency of 23.91%, measured in-house, and a champion efficiency of 24.58%, independently confirmed by the ISFH CalTeC in Germany. The champion efficiency was measured with total area illumination, including screen-printed fingers and busbars.

Epitaxial Lift-Off Technology for Large Size III–V-on-Insulator Substrate

III-V materials can be a very good channel candidate for monolithic 3D (M3D) integration due to the potential of high-performance and lower process temperature as compared with Si, since a low process temperature is crucial to avoid degradation of bottom devices. For III-V M3D integration, material transfer techniques are important, and such processes should be enabled by low process costs on a large wafer scale. In this study, we propose an InGaAs channel transfer technique by wafer bonding, epitaxial lift-off and III-V layers grown on Si substrate. Effective mobility of fabricated MOS HEMTs using transferred InGaAs layer was 1.3 times higher than that of Si MOSFETs. The proposing channel transfer technique would be useful for M3D integration because it provides wafer scalability, cost-effectiveness, back-gate biasing, and etc.

Electrochemical Nanolithography on Silicon: An Easy and Scalable Method to Control Pore Formation at the Nanoscale.

Lithography on a sub-100 nm scale is beyond the diffraction limits of standard optical lithography but is nonetheless a key step in many modern technological applications. At this length scale, there are several possible approaches that require either the preliminary surface deposition of materials or the use of expensive and time-consuming techniques. In our approach, we demonstrate a simple process, easily scalable to large surfaces, where the surface patterning that controls pore formation on highly doped silicon wafers is obtained by an electrochemical process. This method joins the advantages of the low cost of an electrochemical approach with its immediate scalability to large wafers.

(Invited) Monolithically Integrated Gallium Nitride and Silicon Photoelectrode for Efficient and Stable Artificial Photosynthesis

Artificial photosynthesis, i.e., the chemical transformation of sunlight, water, and carbon dioxide into high energy-rich fuels is one of the keys to sustainable carbon-free, storable, and renewable source of energy. Although significant progress has been made for decades, the development of low cost, efficient, long-term stable semiconductor photocatalysts/photoelectrodes has remained challenging for the large-scale practical application of this frontier technology. Recently, gallium nitride (GaN), the semiconductor that has been widely used in LED lighting and power electronics, has emerged as a highly promising material for artificial photosynthesis. With the incorporation of indium, the energy bandgap of GaInN solid solution can be varied across nearly the entire solar spectrum. Significantly, GaInN are the only known semiconductors whose energy band edges can straddle water redox potentials under deep visible and near-infrared light, which is essential for the efficient generation of solar fuels through water splitting and CO2 reduction. We have recently discovered that the surface of III-nitride nanostructures can be tuned to be nitrogen (N)-rich, which can protect against photo-corrosion and oxidation. With the use of such N-rich GaN nanostructures, we have demonstrated the first artificial photosynthesis system that is capable of direct solar water splitting with stability >500 hrs at an efficiency level significantly above the natural photosynthesis. GaN-based nanostructures can be directly integrated with low cost, large area Si wafer. For example, the monolithic integration of an In0.5Ga0.5N top light absorber (energy bandgap ~1. 7 eV) with a Si bottom light absorber (energy bandgap ~1.1 eV) promises a solar-to-hydrogen conversion efficiency up to 30%. We have performed a detailed investigation of the design, synthesis, and photoelectrochemical performance of InGaN/Si double-junction photocathodes. We have demonstrated that InGaN/Si photocathodes can perform unassisted solar water splitting with relatively high efficiency in 0.5 M sulfuric acid under AM1.5G one-sun illumination. Long-term stable operation has also been demonstrated for GaN/Si photocathodes without using any extra surface protection. The unique GaN/Si photoelectrode also provides a powerful platform for the efficient transformation of CO2 to chemical fuels. By coupling with various photocatalysts, the selective conversion of CO2 and water to syngas, methanol, formic acid, and methane has been achieved with high Faradaic efficiency under sunlight illumination. With the use of GaN nanostructures, we have further demonstrated photochemical methanol to ethanol conversion, which enables the direct transition of a toxic fuel (methanol) to a more versatile and safe alternative (ethanol). We will also discuss photochemical nitrogen-fixation on GaN nanostructures, which contributes to the conversion of highly energy-intensive Haber-Bosch industry into mild, clean and sustainable process.

Uniformity improvement of deep silicon cavities fabricated by plasma etching with 12-inch wafer level

The formation of various deep silicon structures using plasma etching has wide applications in sensors, micro-electro-mechanical systems and 3D wafer level integration. However, the fabrication of silicon cavities with high accuracy at depth within a large wafer size is still a challenge due to the large amount of etching required. Herein, silicon cavity etching uniformity approaching 3% in a depth of ~100 µm on a 12-inch wafer is achieved through tuning the focus ring height, baffle shape, double zone helium cooling system and chamber pressure. The simulation of the electromagnetic field and gas flow field separately provides the guidance for the improvement, and the way in which the wafer temperature influences the etch uniformity is demonstrated. These results have significance for both the understanding of the plasma etching mechanism and the practical application of the silicon etching process for advanced device fabrication.

Fluorine boosts graphene growth

To mass-produce technologies that exploit graphene’s exciting electronic and optical properties, manufacturers will need to make large, high-quality films quickly. It turns out that fluorine can help. The gas accelerates graphene growth to more than 1,000 times as fast as without it, researchers report (Nat. Chem. 2019, DOI: 10.1038/s41557-019-0290-1). “The recorded growth rate of 1.2 mm/min could, in principle, allow us to grow a very large graphene wafer in less than 10 min,” says Feng Ding of the Institute for Basic Science in Ulsan, South Korea. Fluorine can also significantly speed the growth of two other promising 2-D electronic materials, tungsten disulfide and hexagonal boron nitride (h-BN). Researchers usually make graphene with chemical vapor deposition (CVD), which involves injecting methane vapors into a heated vacuum chamber, where the gas decomposes and deposits as graphene on copper foil. Recently, researchers have found that adding oxygen or hydrogen into the reactor helps

(Invited) Challenges of Graphene Process Integration in CMOS Technology

In this paper we have investigated various steps of graphene device fabrication in a 200 mm wafer Si technology environment. This work has also introduced some of the key process modules which may pave the way to large-scale manufacturing of hybrid graphene-Si components. Although the demonstrated process flow requires further improvements to increase device yield and reduce variability the practical relevance is emphasized by the facts that first the proposed processes and materials enable efficient encapsulation and low-resistance metal-graphene contacts and secondly they are compatible with those used in the large-scale fabrication of Si-based ICs. Among the key factors which are limiting the performance and yield of the graphene are uniformity after transfer, process-related contaminations, and poor adhesion/delamination of graphene during various processing steps. In fact, availability of clean and uniform graphene layers on large diameter wafers (200/300 mm) can be considered as a critical prerequisite to further progress in the process integration of graphene devices in Si technology environment.

Quantification of the quantum efficiency of radiation of a freestanding GaN crystal placed outside an integrating sphere

An ideal method to quantify the internal quantum efficiency (IQE) of radiation for condensed-matter placed outside an integrating sphere (ϕ-configuration) is demonstrated by showing the data for a freestanding GaN crystal using improved omnidirectional photoluminescence (ODPL) spectroscopy, Kojima et al. [J. Appl. Phys. 120, 015704 (2016)]. The crystal is optically coupled with the sphere through a pinhole fabricated on the sphere, and thus ODPL with ϕ-configuration gives IQE because the light-escaping cone for the crystal defines the observable photoluminescence owing to the large absorption and crystal thickness. This nondestructive ODPL configuration is applicable to large size crystals or semiconductor wafers.

Highly passivating and blister-free hole selective poly-silicon based contact for large area crystalline silicon solar cells

Passivating the contacts of crystalline silicon (c-Si) solar cells with a poly-crystalline silicon (poly-Si) layer on top of a thin silicon oxide (SiOx) is currently sparking interest for reducing recombination at the interface between the metal electrode and the c-Si substrate. Hole-selective poly-Si/SiOx structures could be particularly relevant to passivate the rear side of mass-produced p-type c-Si solar cells (i.e. PERC solar cells). In this study, we elaborate on the optimization of a hole-selective passivating structure consisting of a boron-doped poly-Si layer on top of a chemically grown thin SiOx. The poly-Si layer is prepared by Plasma Enhanced Chemical Vapor Deposition, which enables single-side deposition. However, if not optimized, this deposition technique leads to degradation of the poly-Si layer through a “blistering” phenomenon due to high hydrogen incorporation in the layer. To tackle this, a study of the interplay between process parameters and blistering is undertaken in order to obtain highly passivating and blister-free poly-Si/SiOx structures. By addition of a hydrogenation step, the implied open circuit voltage (iVoc) provided by the structure is further improved, leading to a maximum value of 734 mV demonstrated on symmetrical samples made from large area wafers. We also conduct a Conductive-Atomic Force Microscopy (C-AFM) study with the aim of investigating the pinholes formation in the SiOx interfacial layer that could explain the transport of free charge carriers within the poly-Si/SiOx structure. We show that the current levels detected by C-AFM are affected by an oxide layer that grows at the poly-Si top surface. We also demonstrate that conductive spots detected by C-AFM are not likely to mirror conductive pinholes within the SiOx layer but are rather linked to the poly-Si layer.