Double-Sided Polishing Simulation Based on the Gap Theory - Theory of Pressure Distribution Analysis and Conditions for High Flatness

Abstract

The double sided polishing technique is often applied to achieve high total thickness variance (TTV) of large silicon wafers that are employed to manufacture integrated circuit (IC) cards and smartphones. However, the theoretical analysis of high TTV is not sufficiently studied for the double sided polishing. Whereas, a polishing simulation for single sided polishing based on the gap theory was already developed. This simulation results were compared to the experimental results and indicate good behavior characteristics. This study presents a description of the theory for analyzing pressure distribution for double sided polishing and the simulation results of the surface generation process. It was demonstrated that the average of total running distance is nearly equal for the upper and the lower plates. Improved flatness is obtained when the rotation speed differences of the upper and lower plate rotations for the carrier revolution are equal. Furthermore, it was shown that TTV of less than 0.04 μm with a flatness of less than 0.05 μm may be attained when the cone upper plate with the optimum slope and the flat lower plate are employed with lower carrier rotation.