Large Wafers Research Articles

Ultraviolet line structuring of large solar wafers

AbstractUltrashort‐pulsed lasers are ideal for material processing by welding, marking, and cutting. Scanning systems are crucial for large substrates. We introduce a novel UV line structuring method using deformable mirror technology and freeform optics. This approach aims to improve processing times on large substrates, especially for M12 solar wafer processing. By using a freeform lens and a Zwobbel deformable mirror, we achieve extended processing fields and high scan frequencies. The paper explores optical designs, their robust optomechanical implementation for prototyping, and setup characterization.

Fracture strength analysis of large-size and thin photovoltaic monocrystalline silicon wafers

Diamond wire slicing technology is the main method to manufacture the substrate of the monocrystalline silicon-based solar cells. With the development of technology, the size and thickness of monocrystalline silicon wafer are respectively getting larger and thinner, which cause an increase in silicon wafer fracture probability during wafer processing and post-processing. And the change of the sawing speed, saw wire diameter and abrasive size also affect the wafer’s surface characteristics, thereby affect its fracture strength. In this paper, monocrystalline silicon wafer with large size of 210 mm × 210 mm was taken as the research object, 4-point bending test was carried out on each series of silicon wafers. The load–displacement curves during bending test were collected, and the fracture stress values were calculated by finite element method. The characteristic fracture strength and Weibull modulus of each series of silicon wafers were obtained through the statistical analysis of the data using Weibull distribution function. The effect of the silicon wafer thickness, the position of the silicon wafer in the silicon brick (usage time of the saw wire varies), and the bending test direction on the fracture characteristics was analyzed. The results showed that the increase of thickness increase the characteristic fracture strength of silicon wafer. The characteristic fracture strength of the front wafers (sawn by the fresh wire) is the smallest, while the characteristic fracture strength of the middle wafers and the rear wafers (sawn by the worn wire) are similar. The characteristic fracture strength of bending in the direction of perpendicular to the saw marks is 2–3 times that of bending in the direction of parallel to the saw marks. The reason of the difference of characteristic fracture strength was analyzed based on the surface morphology, roughness, and the saw marks of silicon wafer. In this paper, the fracture characteristics of large size monocrystalline silicon wafer are studied to provide fracture data support for industry production. The mechanism and main effect factors of silicon wafer fracture are revealed, which provides directions for improving the sawing quality and reducing the fracture probability during wafer production process and post-processing.

Microstructural Characterization of InP Films on SOI (001) Substrates Grown by Selective Lateral Metal-Organic Vapor-Phase Epitaxy

To achieve monolithic integration of Si-waveguide-coupled III-V laser diodes, it is important to establish a method of growing high-quality III-V materials on large Si wafers without a thick buffer layer. Here, the lateral aspect ratio trapping (LART) method has recently been attracting attention because of its potential for integrating large-area and high-quality III-V films on (001)-oriented silicon-on-insulator (SOI) substrates. In this paper, we report a detailed microstructural analysis of InP films that were fabricated on (001) SOI substrates by using metal–organic vapor-phase epitaxy and the LART method. The obtained films had an area of around 50 x 4 μm2, which is large enough for them to be used as templates in photonics device fabrication. Transmission electron microscopy revealed that propagation of threading dislocations in the Si/InP interface region was suppressed. However, the films tended to contain other planar defects, such as stacking faults, rotational twin boundaries, and anti- phase boundaries. We discuss the mechanisms underlying the generation of these defects and approaches to suppressing their formation.

A wireless-feeding capacitive electrode mechanism for achieving massive nanosecond parallel-discharge EDM for large-size wafer flattening

The single-crystal silicon carbide (SiC) wafer diameter is increasing beyond 8 in posing significant challenges to conventional mechanical wafer-processing methods. This study presents an innovative capacitive electrode method for electrical discharge flattening (EDF) of as-sliced large 4H-SiC wafers. The capacitive electrode can be divided into near-infinite units, which significantly reduces the working gap capacitance and enables the generation of a mass of parallel discharges with a nanosecond pulse duration (< 200 ns). This approach offers significant advantages in achieving high efficiency and surface finish simultaneously, regardless of the increase in wafer size. This novel electrode design allows wireless electricity feeding via electrostatic induction, which significantly facilitates the integration of parallel electrode units. Furthermore, a sinusoidal voltage is demonstrated for the first time to identify and promote a parallel discharge state. A model was devised to quantitatively describe the overall process. Using this model, the relationship between the gap voltage, discharge energy, and capacitive electrode properties was predicted, revealing a parallel discharge mechanism. The capacitive electrode mechanism was validated via EDF experiments on a 4H-SiC wafer. Notably, >33 parallel discharges within 6 μs were achieved in a single pulse, resulting in a minimum discharge energy of 0.312 μJ (peak current: 0.18 A, duration: 160 ns) and a surface roughness of Ra 42 nm. Moreover, a machining speed of 0.5 μm/min was achieved on a 4 in wafer, representing an improvement of an order of magnitude compared to conventional non-parallel discharge methods.

Optimizing Ti/TiN Multilayers for UV, Optical and Near-IR Microwave Kinetic Inductance Detectors

Microwave Kinetic Inductance Detectors (MKIDs) combine significant advantages for photon detection like single photon counting, single pixel energy resolution, vanishing dark counts and µs time resolution with a simple design and the feasibility to scale up into the megapixel range. But high quality MKID fabrication remains challenging as established superconductors tend to either have intrinsic disadvantages, are challenging to deposit or require very low operating temperatures. As alternating stacks of thin Ti and TiN films have shown very impressive results for far-IR and sub-mm MKIDs, they promise significant improvements for UV, visible to near-IR MKIDs as well, especially as they are comparably easy to fabricate and control. In this paper, we present our ongoing project to adapt proximity coupled superconducting films for photon counting MKIDs. Some of the main advantages of Ti/TiN multilayers are their good control of critical temperature (Tc) and their great homogeneity of Tc even over large wafers, promising improved pixel yield especially for large arrays. We demonstrate the effect different temperatures during fabrication have on the detector performance and discuss excess phase noise observed caused by surface oxidization of exposed Si. Our first prototypes achieved photon energy resolving powers of up to 3.1 but turned out to be much too insensitive. As the work presented is still in progress, we also discuss further improvements planned for the near future.

Status of h-BN quasi-bulk crystals and high efficiency neutron detectors

III-nitrides have fomented a revolution in the lighting industry and are poised to make a huge impact in the field of power electronics. In the III-nitride family, the crystal growth and use of hexagonal BN (h-BN) as an ultrawide bandgap (UWBG) semiconductor are much less developed. Bulk crystals of h-BN produced by the high-temperature/high-pressure and the metal flux solution methods possess very high crystalline and optical qualities but are impractical to serve as substrates or for device implementation as their sizes are typically in millimeters. The development of crystal growth technologies for producing thick epitaxial films (or quasi-bulk or semi-bulk crystals) in large wafer sizes with high crystalline quality is a prerequisite for utilizing h-BN as an UWBG electronic material. Compared to traditional III-nitrides, BN has another unique application as solid-state neutron detectors, which however, also require the development of quasi-bulk crystals to provide high detection efficiencies because the theoretical efficiency (ηi) relates to the detector thickness (d) by ηi=1−e−dλ, where λ denotes the thermal neutron absorption length which is 47 μm (237 μm) for 10B-enriched (natural) h-BN. We provide an overview and recent progress toward the development of h-BN quasi-bulk crystals via hydride vapor phase epitaxy (HVPE) growth and the attainment of thermal neutron detectors based on 100 μm thick 10B-enriched h-BN with a record efficiency of 60%. The thermal neutron detection efficiency was shown to enhance at elevated temperatures. Benchmarking the crystalline and optical qualities of h-BN quasi-bulk crystals with the state-of-the-art mm-sized bulk crystal flakes and 0.5 μm thick epitaxial films identified that reducing the density of native defects such as vacancies remains the most critical task for h-BN quasi-bulk crystal growth by HVPE.

Study of AlScN thin film deposition on large size silicon wafer

This work prepared Al0.8Sc0.2N thin films (AlScN) with a thickness of 1 μm on Φ = 200 mm (100) bare silicon wafers and studied the effects of sputtering power, substrate bias power and gas flow on the quality of films. The microstructure, crystal orientation and piezoelectric response of the AlScN thin films were comprehensively investigated. The prepared films exhibit highly c-axis texture and smooth surface on large size wafers, which meet with the requirement of massive production of micro-electro-mechanical system devices. The best full width half maximum of 1.34° was obtained in the films deposited with the sputtering power of 4 kW. Substrate bias power can enable the film to achieve stress close to 0 without obviously deteriorating other properties. N2 flow ratio has the greatest impact on the c-axis texture and surface morphology of AlScN films. Lower N2 flow ratio will promote the generation of surface abnormal oriented grains, resulting in the degradation of (002) orientation of AlScN and surface roughness, thereby deteriorating the piezoelectric performance of the film. N2 ratio greater than 60 % and compressive stress are preferred for the deposition of AlScN piezoelectric films.

Study on the Manufacturability of X Dimension Fan Out Integration Package with Organic RDLs (XDFOI-O)

The concept of chiplet was proposed in the post- Moore era. How to layout the multiple chips with different processes and sizes in the package structure is a problem that needs to be considered as different layouts may significantly affect the manufacturability during the packaging process. XDFOI-O is a 2.5D organic interposer structure with a significant coefficient of thermal expansion mismatch in it. Different layouts may cause excessive stress concentration in the package structure, as well as large wafer warpage, which can affect the normal operations of the production line. Stress accumulation on specific chiplet during the wafer thinning process is another manufacturability problem, leading to chip cracking. Prospective finite element analysis can be applied to evaluate the various layouts. In simulation work, different placement processes of dummy chips as stiffeners, as well as different chiplet thicknesses and underfill coverage, can be used as factors for simulation studies, thereby making a reference for further chiplet package design.

(Invited) Application of 3D in-Situ X-Ray Visualization to Track the Formation of Dislocation Clusters during PVT Growth of SiC

SiC has become the key player among wide bandgap semiconductors for power electronic applications. Since the first description of the physical vapour transport (PVT) growth process of SiC by Tairov and Tsvetkov (J. Crystal Growth, 43, 209(1978)), there has been steady progress in SiC-based crystal growth, epitaxy and device processing. The success of SiC compared to Si is related to its superior material properties such as extremely high electrical breakdown field and high thermal conductivity compared to the standard silicon counterpart. In addition, SiC device processing utilises much of the standard Si processing equipment. A major reason for the success of SiC in power electronic applications compared to other wide bandgap counterparts such as GaN, Ga2O3 and diamond is related to the availability of large diameter SiC wafer materials (150mm = standard, 200mm = developped). Bulk SiC growth is now a very well developed process with comparatively high yields. The extraordinary physical properties also include obstacles related to the strong chemical bonding and complex phase diagram of the material, which pose challenges to the growth process. Therefore, there are still a number of open questions related to the nucleation, progression and termination of the bulk growth process that require fundamental research in materials science and technology.The aim of this presentation is (i) to give an overview of the state-of-the-art PVT growth process and (ii) to discuss a current research topic dealing with the early stage of the growth process and the defect formation that can occur during the initial nucleation of SiC. We have applied 3D in-situ visualisation of the growth process using X-ray computed tomography to visualise island formation on the large seeding area. These data are related to growth process instabilities such as temperature variations during the seeding process and axial doping level changes from the seed to the newly grown crystal. Both process instabilities induce mechanical stress on the SiC lattice and act as sources for dislocation generation and multiplication. We will show a series of growth processes with varying growth parameters that shed light on the initial growth stage of SiC.As the crystal diameter of SiC increases from 150 mm to 200 mm, the results of this study become increasingly important.

Retesting Schemes That Improve Test Quality and Yield Using a Test Guardband

The digital integrated circuit (IC) testing model module is applied in this study to simulate the fabrication and testing of integrated circuits. The yield and quality of ICs are analyzed by assuming that the wafer devices under test conditions are normal probability distributions. The difficulties of testing and verification become increasingly great as the design function of the chip becomes remarkably complex. Conversely, the automotive industry chip supply chain has been substantially affected since the COVID-19 outbreak. The shortage of chips in the auto-market has always existed; therefore, increasing available chips under a limited production capacity has become a top priority. Therefore, this study applies the digital integrated circuit testing model (DITM) and proposes a retest plan. This method does not require considerable time to collect large wafer data, nor does it require additional hardware equipment. Furthermore, the required test quality parameters are set, and the test is repeated on the device by adjusting the test guardband (TGB). Moreover, three retesting schemes are proposed to improve the IC test quality (Yq) and test yield (Yt) to meet the requirements of consumers for product quality. A set of 2021 IEEE International Roadmap for Devices and Systems (IRDS) parameters is used to demonstrate the three proposed retesting schemes. The simulation results from the 2021 IRDS data prove that the retest method can effectively improve the test yield (Yt). A comparison of the estimated results of the three retest methods shows that using the repeat test method can maximize the test yield without sacrificing the test quality (Yq). By contrast, repeat testing can indeed improve the test yield (Yt) by 14% or more. Moreover, the increase in sellable ICs not only increases additional earnings for corporations, but also alleviates the current global shortage of automotive ICs.

Development and analysis of thick GaN drift layers on 200 mm CTE-matched substrate for vertical device processing

This work reports the epitaxial growth of 8.5 µm-thick GaN layers on 200 mm engineered substrates with a polycrystalline AlN core (QST by QROMIS) for CMOS compatible processing of vertical GaN power devices. The epitaxial stack contains a 5 upmum thick drift layers with a Si doping density of 2 × 1016 cm−3 and total threading dislocation density of 4 × 108 cm−2. The thick drift layer requires fine-tuning of the epitaxial growth conditions to keep wafer bow under control and to avoid the formation of surface defects. Diode test structures processed with this epitaxial stack achieved hard breakdown voltages > 750 V, which is shown to be limited by impurity or metal diffusion from the contact metal stack into threading dislocations. Conductive Atomic Force Microscopy (cAFM) reveals some leakage contribution from mixed type dislocations, which have their core structure identified as the double 5/6 atom configuration by scanning transmission electron microscopy images. Modelling of the leakage conduction mechanism with one-dimensional hopping conduction shows good agreement with the experimental data, and the resulting fitting parameters are compared to similar findings on silicon substrates. The outcome of this work is important to understand the possibilities and limitations of vertical GaN devices fabricated on large diameter wafers.

High-speed and high-precision control of laser stealth dicing equipment based on interpolation and fitting

As an advanced wafer dicing technology, stealth dicing has the advantage of better-cutting quality and faster-cutting speed than traditional blade dicing technology and has a broad application prospect for the future cutting of large and ultra-thin silicon wafers. The stealth dicing equipment involves two processes, i.e., wafer altimetry and follow-through processing in silicon wafer cutting, the altimetry accuracy of which determines the processing precision. In this paper, polynomial fitting, linear interpolation, and cubic spline interpolation are applied to predict the altimetry data at different speeds to achieve high-speed and high-precision altimetry under various speed conditions. The research shows that the prediction accuracy of the three methods is less than 1 μm. The linear interpolation has the highest accuracy during the altimetry speeds of 500 mm/s ~ 1500 mm/s. The polynomial fitting can achieve better prediction results by selecting the best fitting parameter when the altimetry speeds are 1500 mm/s ~ 2500 mm/s. The cubic spline interpolation is more suitable for the processing of data sampled at altimetry speeds between 2500 mm/s and 3000 mm/s.

Probing Boron Vacancy Complexes in h-BN Semi-Bulk Crystals Synthesized by Hydride Vapor Phase Epitaxy

Hexagonal BN (h-BN) has emerged as an important ultrawide bandgap (UWBG) semiconductor (Eg~6 eV). The crystal growth technologies for producing semi-bulk crystals/epilayers in large wafer sizes and understanding of defect properties lag decades behind conventional III-nitride wide bandgap (WBG) semiconductors. Here we report probing of boron vacancy (VB)-related defects in freestanding h-BN semi-bulk wafers synthesized by hydride vapor phase epitaxy (HVPE). A photocurrent excitation spectroscopy (PES) was designed to monitor the transport of photoexcited holes from deep-level acceptors. A dominant transition line at 1.66 eV with a side band near 1.62 eV has been directly observed, which matches well with the calculated energy levels of 1.65 for the VB-H deep acceptor in h-BN. The identification of VB complexes via PES measurement was further corroborated by the temperature-dependent dark resistivity and secondary ion mass spectrometry measurements. The results presented here suggested that it is necessary to focus on the optimization of V/III ratio during HVPE growth to minimize the generation of VB-related defects and to improve the overall material quality of h-BN semi-bulk crystals. The work also provided a better understanding of how VB complexes behave and affect the electronic and optical properties of h-BN.

In‐Plane 1.5 µm Distributed Feedback Lasers Selectively Grown on (001) SOI

AbstractHetero‐epitaxy for integration of efficient III‐V lasers on silicon can enable wafer‐scale silicon photonic integrated circuits, which can unleash the full advantages of silicon photonics in production on large silicon wafers with low cost, high throughput, and large bandwidth and large‐scale integration. In this work, efficient III‐V distributed feedback (DFB) lasers selectively grown on (001) silicon‐on‐insulator (SOI) wafers are presented. The selective hetero‐epitaxy of sufficiently large areas of III‐V segments allows the demonstration of DFB lasers on the SOI wafer. The fabricated DFB lasers feature a co‐planar configuration with the Si layer, allowing for efficient coupling between III‐V lasers and Si waveguides. The unique III‐V‐on‐insulator structure also provides strong optical confinement for the lasers. Gratings are designed and fabricated with minimal non‐radiative recombination and a simple process with good tolerance. The optically pumped DFB laser has a low lasing threshold of around 17.5 µJ cm−2, stable single‐mode lasing at 1.5 µm, a side‐mode‐suppression‐ratio of over 35 dB, and a spontaneous emission factor of 0.7. The results here demonstrate a step forward towards wafer‐scale integration with monolithically grown lasers, thus outlining the prospect of fully integrated Si photonics.

Determination of the Equivalent Thickness of a Taiko Wafer Using ANSYS Finite Element Analysis

The successful handling of large semiconductor wafers is crucial for scaling up their production. Early-stage warpage control allows the prevention of undesirable asymmetric warpage, known as wafer bifurcation or buckling. Indeed, even in a gravity-free environment, thinning an 8″ or 12″ semiconductor wafer can result in warpage and bifurcation. To mitigate this issue, the taiko method, which involves creating a thicker ring region around the rim of the wafer, has been widely used. Previous research has focused on the theoretical factors affecting the warpage of a backside metalized taiko wafer. This work extends the case to a front-side metalized taiko wafer and introduces the concept of the equivalent thickness of a taiko wafer. The equivalent thickness of a taiko wafer, influenced by the ring region, lies in between the thickness of the central region and that of the annular region. Because of the limited number of taiko wafers that can be produced on a production line, modelling can be beneficial. In this work we compared the results of a developed analytical model with those obtained from a finite element analysis (FEA) approach with ANSYSY® Mechanical Enterprise 2022/R2 software to model the equivalent thickness of a taiko wafer. We investigated the curvature as a function of the stress of the metal layer, considering key design factors such as the substrate region thickness, the thickness of the thin metal film, the step height, and the width of the ring region. By systematically varying the thickness of the central region of the taiko wafer, we explored the curvature as a function of stress induced by thermal load in the linear regime and determined the slopes in the linear region of the curvature vs. stress curves. The aim of this study is to identify regularities and similarities with the Stoney equation and investigate the validity of the analytical approach for the case of a taiko substrate. The results show that there is a good agreement between the analytical model of a taiko wafer and the numerical analysis gained by the FEA methods.

Characteristics, application and development trend of the third-generation semiconductor

Various devices made of the third-generation semiconductor have been gradually applied to various fields with the rapid development of the third-generation semiconductor materials equipment, manufacturing technology, and device physics represented by SiC and GaN. Firstly, the characteristics of the third-generation semiconductors is analyzed in this paper. Compared with the first-generation and second-generation semiconductors, the third-generation semiconductor has a wider band gap width, higher breakdown electric field, higher thermal conductivity, higher electron saturation rate and more expensive price. Then this paper will talk about the application of the third-generation semiconductor. The third-generation semiconductor materials can be mainly used in three fields, which are photoelectric, microwave radio frequency and power electronics. In terms of the photoelectric aspect, this paper takes the blue LED as an example. The blue LED is produced because of the wide band gap of the third-generation semiconductor. In the microwave RF aspect, the paper takes the 5G communication system as an example. Third-generation semiconductors make the high-frequency, high-power devices needed for 5G communications systems. In the power electronics aspect, the paper cites new energy vehicles as an example. Third-generation semiconductor components have a number of features needed for new-energy vehicles. For example, third-generation semiconductors can work at high temperatures. Finally, this paper will introduce the development trend of it. In the future, larger wafers will become mainstream. The third-generation semiconductors will be used in more fields. In addition, the new material systems will gradually mature.

Annealing-Modulated Surface Reconstruction for Self-Assembly of High-Density Uniform InAs/GaAs Quantum Dots on Large Wafers Substrate.

In this work, we developed pre-grown annealing to form β2 reconstruction sites among β or α (2 × 4) reconstruction phase to promote nucleation for high-density, size/wafer-uniform, photoluminescence (PL)-optimal InAs quantum dot (QD) growth on a large GaAs wafer. Using this, the QD density reached 580 (860) μm-2 at a room-temperature (T) spectral FWHM of 34 (41) meV at the wafer center (and surrounding) (high-rate low-T growth). The smallest FWHM reached 23.6 (24.9) meV at a density of 190 (260) μm-2 (low-rate high-T). The mediate rate formed uniform QDs in the traditional β phase, at a density of 320 (400) μm-2 and a spectral FWHM of 28 (34) meV, while size-diverse QDs formed in β2 at a spectral FWHM of 92 (68) meV and a density of 370 (440) μm-2. From atomic-force-microscope QD height distribution and T-dependent PL spectroscopy, it is found that compared to the dense QDs grown in β phase (mediate rate, 320 μm-2) with the most large dots (240 μm-2), the dense QDs grown in β2 phase (580 μm-2) show many small dots with inter-dot coupling in favor of unsaturated filling and high injection to large dots for PL. The controllable annealing (T, duration) forms β2 or β2-mixed α or β phase in favor of a wafer-uniform dot island and the faster T change enables optimal T for QD growth.

Unlocking the monolithic integration scenario: optical coupling between GaSb diode lasers epitaxially grown on patterned Si substrates and passive SiN waveguides

Silicon (Si) photonics has recently emerged as a key enabling technology in many application fields thanks to the mature Si process technology, the large silicon wafer size, and promising Si optical properties. The monolithic integration by direct epitaxy of III–V lasers and Si photonic devices on the same Si substrate has been considered for decades as the main obstacle to the realization of dense photonics chips. Despite considerable progress in the last decade, only discrete III–V lasers grown on bare Si wafers have been reported, whatever the wavelength and laser technology. Here we demonstrate the first semiconductor laser grown on a patterned Si photonics platform with light coupled into a waveguide. A mid-IR GaSb-based diode laser was directly grown on a pre-patterned Si photonics wafer equipped with SiN waveguides clad by SiO2. Growth and device fabrication challenges, arising from the template architecture, were overcome to demonstrate more than 10 mW outpower of emitted light in continuous wave operation at room temperature. In addition, around 10% of the light was coupled into the SiN waveguides, in good agreement with theoretical calculations for this butt-coupling configuration. This work lift an important building block and it paves the way for future low-cost, large-scale, fully integrated photonic chips.

Silicon Carbide Power Devices: Progress and Future Outlook

Silicon Carbide (SiC) power devices have become commercialized and are being adopted for many applications after 40 years of effort to produce large diameter wafers and high performance device structures. This paper provides a historical perspective of the key breakthroughs that were needed to make progress towards this goal. The JBS rectifier concept was a critical innovation required to make SiC power Schottky rectifiers viable. The Baliga-Pair or Cascode concept was an intermediate step to realize a practical SiC power switch in the 1990s. An essential unique innovation created in the 1990s was the shielded planar SiC power MOSFET structure that is now commonly used for commercial products. Shielded trench-gate SiC power MOSFETs were also proposed in the 1990s which led to commercial products in the last 5 years. Although achieving a low specific on-resistance in SiC power MOSFETs was essential at the inception of the technology, its penetration into power electronics applications is now driven by performance metrics for high frequency circuits. Device structural enhancements to improve the high frequency figures-of-merit are described that have led to major strides in performance. This includes the JBSFET concept where a JBS diode is integrated into the MOSFET structure to suppress current flow through the body diode; the SG and BG MOSFET structures which reduce the gate-drain charge; and the OCTFET structure where the gate-drain overlap area is reduced. Future developments in SiC power devices include increasing the blocking voltage rating to expand the applications spectrum. In addition, a SiC monolithic bi-directional switch has been demonstrated to allow implementation of matrix converters; and a SiC monolithic reverse blocking switch has been demonstrated to allow deployment of current source inverters.

Effects of grinding-induced surface topography on the material removal mechanism of silicon chemical mechanical polishing

Ultra-precision thinning technology using workpiece self-rotational grinding followed by chemical mechanical polishing (CMP) is extensively applied in the integrated circuit manufacturing process, which enables to obtain large size ultra-thin silicon wafers with high material removal rate and low damage layer thickness. However, an in-depth understanding of the influence caused by ground surface topography on material removal mechanism in silicon CMP process has not been revealed yet. This work systematically investigates the contact characteristics of the wafer-pad interface and corrosion behaviors of the ground silicon wafer immersed in polishing solution. Firstly, some silicon wafers are ground using different wheels and subsequently polished. The material removal depth during the whole CMP process is measured. Then, the intrinsic model of polishing pad is determined via mechanical property tests. A finite element method is adopted to evaluate the contact status, displacement distortion and stress distribution at the contact region between pad and ground wafer surface. Moreover, the chemical reaction mechanism between ground silicon wafer and polishing solution is revealed by utilizing X-ray photoelectron spectroscopy and electrochemical analysis. The influence of wafer surface topography on corrosion resistance in CMP process is illustrated. Finally, corresponding experimental results are explained from an atomic scale by a ReaxFF reactive molecular dynamics simulation model. This presented study demonstrates the corrosion promotion principle of ground silicon wafer in CMP process.