Large Scale Integration Process Research Articles

Low temperature grown carbon nanotube interconnects using inner shells by chemical mechanical polishing

Vertically aligned multiwalled carbon nanotubes (MWCNTs) were synthesized by remote plasma chemical vapor deposition at a low temperature of 390°C, which meets the requirement of the large scale integration (LSI) process. For wiring application, we measured the electrical properties of MWCNT-via structures with and without chemical mechanical polishing (CMP). The via resistances were reduced using inner shells of MWCNTs whose caps were opened due to CMP. The improved resistance after annealing at 400°C was 0.6Ω for 2μm vias. Our process is suitable for LSI because the temperature never exceeds the allowable temperature of 400°C in the Si LSI process.

Performance-Driven Crosstalk Elimination at Postcompiler Level—The Case of Low-Crosstalk Op-Code Assignment

Significant advances in very large-scale integration process technology have scaled the feature size down. One effect of this scaling down is that coupling capacitances have grown reciprocal in the square of the scaling factor. This crosstalk effect will not only increase the power consumption but also lengthen the propagation delay. Since the data sequences on an instruction bus are known during the compile time, this paper presents two compiler algorithms, rescheduling and renaming, for performance improvement by eliminating crosstalk effects on an instruction bus. The results show that our crosstalk-eliminating postcomplier algorithms significantly reduce the dynamic instruction overhead from 11.50% to 0.52% by eliminating the 4middotC crosstalk. Due to the effective 4middotC crosstalk elimination, our proposed method can improve the instruction fetch time up to 9.59%

Single-Electron Transistor (SET) Process and Device Simulation Using SYSNOPSYS TCAD Tools

Simulation of semiconductor device fabrication and operation is important to the design and manufacture of integrated circuits because it provides insights into complex phenomena that cannot obtained through experimentation or simple analytic models. Process and device simulation is commonly using for the design of new very large scale integration (VLSI) devices and processes. Simulation programs serves as exploratory tools in order to gain better understanding of process and device physics. In this research, single-electron transistor (SET) is simulated using Synopsys TCAD simulation tools to improve device performance and reliability or to increase the yield. The Taurus Medici is utilized for SET device simulation and the SET process simulation is utilizing Taurus TSUPREM-4. In addition, the structure of SET device, the capacitance, power, resistance and charging energy of SET device were obtained from these simulations. Ultimately, the SET device is operated at room temperature operation (300K).

Profile-guided microarchitectural floor planning for deep submicron processor design

As very large scale integration (VLSI) process technology migrates to nanoscale with a feature size of less than 100 nm, global wire delay is becoming a major hindrance in keeping the latency of intrachip communication within a single cycle, thus substantially decaying performance scalability. In addition, an effective microarchitectural floor planning algorithm can no longer ignore the dynamic communication patterns of applications. This article, using the profile information acquired at the microarchitecture level, proposes a "profile-guided microarchitectural floor planner" that considers both the impact of wire delay and the architectural behavior, namely, the intermodule communication, to reduce the latency of frequent routes inside a processor and to maintain performance scalability. Based on the simulation results here, the proposed profile-guided method shows a 5%-40% average instructions per cycle (IPC) improvement when the clock frequency is fixed. From the perspective of instruction throughput in billion instructions per second (BIPS), the floor planner is much more scalable than the conventional wirelength-based floor planner.

Power feasibility of implantable digital spike sorting circuits for neural prosthetic systems

A new class of neural prosthetic systems aims to assist disabled patients by translating cortical neural activity into control signals for prosthetic devices. Based on the success of proof-of-concept systems in the laboratory, there is now considerable interest in increasing system performance and creating implantable electronics for use in clinical systems. A critical question that impacts system performance and the overall architecture of these systems is whether it is possible to identify the neural source of each action potential (spike sorting) in real-time and with low power. Low power is essential both for power supply considerations and heat dissipation in the brain. In this paper we report that state-of-the-art spike sorting algorithms are not only feasible using modern complementary metal oxide semiconductor very large scale integration processes, but may represent the best option for extracting large amounts of data in implantable neural prosthetic interfaces.

Reliability of HfSiON gate dielectrics

The reliability of ultra-thin (1.38 nm–2.14 nm EOT) hafnium silicate gate dielectrics was studied to determine their suitability for incorporation into large-scale integration processes at sub-100 nm channel length. The reliability study includes a discussion of the evolution of current with time during a constant voltage stress, deduction of Weibull slopes, voltage acceleration and an estimate of the 10-year maximum operating voltage for devices fabricated with these layers. Finally, the change in Weibull slope at increased current step magnitude for constant voltage stress is used to observe the change in trap generation rate during a CVS until breakdown.

The Effect of Annealing Temperatures on Self-Aligned Replacement (Damascene) TaCN–TaN-Stacked Gate pMOSFETs

In this paper, we report the first self-aligned replacement (Damascene) TaCN-TaN-stacked gate electrode pMOSFETs. The high-temperature (>1000/spl deg/C) implant activation anneal was done prior to the metal electrode deposition. After the fabrication was completed, the transistors were then annealed at lower temperatures (300/spl deg/C-600/spl deg/C), which might affect the critical device parameters, such as subthreshold slope, threshold voltage, gate leakage, on, and off currents. Our data show that TaCN is a promising material for the metal-gate pMOSFETs due to the suitable metal work function and good thermal stability up to 500/spl deg/C, which is much higher than the highest temperature required by the backend very large-scale integration process.

Defect reduction in Cu dual damascene process using short-loop test structures

This paper outlines the defect reduction measures performed during the development of a 130-nm Cu dual-damascene process. The test methodology, using short-loop test structures, included defect tracing, overlaying defect data and electrical measurement data, physical analyses based on these results, and analyses of defect size distribution. While the defect size distributions for large-scale integration processes are considered to depend on x/sup -k/, the distribution for the Cu dual-damascene process is found to be different and is instead characterized by a cumulative distribution described by the composition of several Lorentzian functions. Using these procedures, defect densities were successfully reduced by 50% in half the time taken previously and without the need for actual products.

New atomic force microscopy imaging for an inline large scale integration process monitor

New imaging techniques in atomic force microscopy have been developed to suppress bending of the sharpened probe during scanning. After analyzing the bending of the probe, it is clear that the bending is caused by response of servo control and slip of the probe on the slope. It is essential that we do not scan the probe under contact on a sample surface and we approach the surface at a contact force of <10 nN for slip-free operation. The technique controls the probe such that approaching and gap-controlling are done without scanning after the probe has been stepped from pixel to pixel, and the step movement is done after lifting the probe up from the sample surface without servo controlling. This technique permits us to use a very sharpened and slim probe so that we can observe a steep structure, such as a dry-etched groove and hole, and a photoresist pattern with a high aspect ratio faithfully. We clarify that it is possible to apply this technique to monitoring the steep structures with an inline process monitor in the large scale integration process without cracking the wafer.

Progress in projection and large-area displays

A new class of compact high-definition electronic projection systems has emerged that are based on microdisplays. Very large scale integration process technology is adapted to fabricate the three classes of microdisplays: (1) transmissive liquid crystal on high-temperature polysilicon/quartz; (2) microelectromechanical devices on silicon; (3) and reflective liquid crystal on silicon. A variety of system architectures are discussed. Key ancillary technologies include small arc lamps, color separation and recombination optics, and rear-projection screens.

Low Loss All-Silicon Single Mode Optical Waveguide with Small Cross-Section

The realization of single-mode rib waveguides in standard epitaxial silicon layer on lightly-doped silicon substrate, using ion-implantation to form the lower cladding, is reported. The waveguides were designed with a cross-section comparable in size to the mode-field-diameter of standard single-mode optical fiber, so reducing the fiberwaveguide coupling losses. Propagation losses of about 1.0 dB/cm, for λ = 1.3 μm, in the single mode regime, have been measured. Numerical evaluation of the theoretical attenuation and the transverse optical field profiles has been performed, both for λ = 1.3 μm and λ = 1.55 μm. The proposed technique is low-cost, fully compatible with standard very large scale integration (VLSI) processes.

Simplified logic for first-order and second-order mismatch-shaping digital-to-analog converters

Mismatch-shaping digital-to-analog converters (DACs) have become widely used in high-performance delta-sigma data converters because they facilitate delta-sigma modulators with multibit quantization. Relative to single-bit quantization, multibit quantization significantly relaxes the analog circuit performance necessary to achieve a given level of data converter precision, but significant digital logic is required to perform the mismatch shaping. In modern very large scale integration processes optimized for digital circuitry, this tends to be a good tradeoff in terms of both area and power consumption. It is nonetheless desirable to minimize the digital complexity as much as possible. Moreover, in delta-sigma analog-to-digital converters the mismatch-shaping logic is in the feedback path of the delta-sigma modulator, so it is essential to maintain a sufficiently small propagation delay through the mismatch-shaping logic. This paper presents and analyzes several variations of the switching blocks within a tree-structured mismatch-shaping DAC that result in the most hardware-efficient first-order and second-order mismatch-shaping DAC implementations yet known to the authors. The variations presented allow designers to tradeoff complexity for propagation-delay reduction so as to tailor designs to specific applications.

Experimental Study of the Degradation of Mechanical Strength of Silicon Wafers Caused by Large Scale Integration Processes

The historical change of mechanical strength of silicon wafer during the large scale integration (LSI) fabrication process has been studied. It was confirmed that the major factor which determines the strength of the bulk crystal is the bulk microdefect (BMD) density in the metal oxide semiconductor field effect transistor fabrication process with local oxidation of silicon (LOGOS) isolation. Unfortunately, the LOGOS fabrication process increases the BMD density and reduces the wafer strength. Further, this study revealed that the ion implantation process induces the most serious degradation of the mechanical strength in the surface region of the Si substrate in the LSI fabrication processes. Whether or not this deterioration in strength is recovered depends on the status of ion implantation and the method of subsequent annealing. The deterioration of strength was caused by ion implantation due to the effect of interstitial silicon atoms and their clusters in a low dose situation (<1014 cm−2), and the amorphous layer or surface roughness in a high dose condition (>1015 cm−2). In order to reduce the crystal defects or wafer‐slips, attention should be paid to the procedural steps which cause reduction in the mechanical strength of silicon crystals while designing the LSI fabrication process.

Fabrication of Si Nanostructures for Single Electron Device Applications by Anisotropic Etching

Si nanostructures for single electron device applications are successfully fabricated using a newly developed anisotropic etching technique . The minimum size of the Si nanostructures is about 10 nm, which is much smaller than the lithography limit. The novel process involves two anisotropic etching steps and one selective oxidation step, and is fully compatible with very large scale integration (VLSI) processes. Scanning electron microscopy (SEM) and atomic force microscopy (AFM) observations indicate that the fabricated nanostructures are very uniform and atomically controlled. This process is promising for the future integration of single electron devices into VLSI chips.

Planarized Copper Multilevel Interconnections for ULSI Applications

As the degree of large-scale integration (LSI) increases, the area of a single transistor will diminish and the density of transistors will increase. Accordingly, technology for high-density wiring to interconnect the huge number of transistors is needed because transistors cannot perform any useful functions without interconnects and electrodes. For advanced microprocessor chips with a sub-half-micron design rule and at least four interconnect layers, the minimum width of the interconnects becomes less than 0.35 μm.Aluminum or an aluminum alloy is now generally used as the interconnect material in LSI circuits because the physical and chemical properties of aluminum are compatible with current LSI processing: Aluminum forms a thin protective oxide film that withstands various thermal processes; it has relatively low electrical resistivity and halide compounds with a relatively high vapor pressure which are suitable for reactive ion etching (RIE), and it is an inexpensive material. The reliability of aluminum interconnects, however, is a major concern for maintaining the total reliability of advanced LSI. Because of its relatively low melting point, aluminum as an interconnect material is susceptible to stress- and electromigration, which leads to open failure of the interconnect. It is well-known that these failure modes are accelerated by decreasing the width and thickness of the interconnects. Hence, use of aluminum interconnects may be limited for future sub-half-micron LSIs.

HIGH‐ORDER POSITIVE, MONOTONE AND CONVEX MULTIGRID INTERPOLATIONS

We develop new high‐order positive, monotone and convex interpolations, which are to be used in the multigrid context. This means that the value of the interpolant is calculated only at the midpoints lying between the locations of the given values. As a consequence, these interpolants can be calculated very efficiently. They are then tested in a time‐dependent very large scale integration process simulation application.

Criteria for use of electron beam charging technique for very large scale integration process inspection

A mathematical description of the method of testing by electron beam charging is used to clearly specify its measurement capabilities. The scanning electron microscopy parameters of beam current, frame scan time, and magnification, are used to derive the requirements necessary to distinguish between shorted and isolated structures.

Design and application of the interlayer van der Pauw resistor alignment bridge

The interlayer van der Pauw (VDP) resistor alignment bridge combines the sheet resistor and registration-sensitive bridge into one unified structure. As a result of symmetry, it does not require the width corrections resulting from image exposure and etch variations typical of linear resistor structures. It uses minimum area and pad count and provides orthogonal registration measurements. Bridges designed for 1.5- mu m feature size with body dimensions of 18 and 21 mu m and a tap length to width ratio of 0.5 show a sensitivity of 34-38 mV/ mu m at 10 mA. Registration errors of 0.2 mu m have been measured with an error of less than 10%. A good statistical correlation has been obtained between drawn and measured registration offsets. The correlation between the VDP bridge and the optical vernier is within +or-2% using a vernier spacing of 0.125 mu m. These results clearly indicate that the VDP bridge has the potential to provide accurate measurements of photo mask registration with the precision required for very large scale integration (VLSI) processing. The application of the VDP resistor bridge for interlayer registration using standard production procedures is described. Measurement precision and accuracy are discussed along with some fundamental bridge-design considerations.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Multielement ultratrace analysis of molybdenum with high performance secondary ion mass spectrometry

Electron beam melting has been used to obtain ultrapure refractory metals that are gaining importance in metal oxide semiconductor-very large scale integration (MOS-VLSI) processing technology, fusion reactor technology, or as superconducting materials. Although the technology of electron beam melting is well established in the field of production of very clean refractory metals, little is known about the limitations of the method because the impurity level of the final products is frequently below the detection power of common methods for trace analysis. Characterization of these materials can be accomplished primarily by in situ methods like neutron activation analysis and mass spectrometric methods [glow discharge mass spectrometry (GDMS), secondary ion mass spectrometry (SIMS)]. A suitable method for quantitative multielement ultratrace bulk analysis of molybdenum with SIMS has been developed. Detection limits of the analyzed elements from 10−7g/gdown to 10−12g/g have been found. Additional information about the distribution of the trace elements has been accumulated.

Rapid Annealing Using Halogen Lamps

A few seconds halogen lamp annealing (HLA) technology is evaluated from the viewpoint of practical application to complementary metal oxide semiconductor (CMOS) very large scale integration (VLSI) processing. , 11B, and 31P ion‐implanted silicon layers have been investigated on their isothermal short‐time annealing behavior of junction leakage current, recrystallization, activation, and junction depth. We have found that a few seconds annealing of 800°C is enough to crystalline regrow the or 31P ion‐implanted amorphous layer, to activate or 31P ion‐implanted dopants, to form titanium silicide, and to reduce the area leakage current of both n+‐p− and p+‐n− junctions without dopant diffusion. But activation of 11B+ ion‐implanted dopants, reduction of perimeter leakage current, molybdenum silicide formation, and phosphosilicate glass (PSG) reflow require a little higher temperature heat‐treatment.