Abstract
The reliability of ultra-thin (1.38 nm–2.14 nm EOT) hafnium silicate gate dielectrics was studied to determine their suitability for incorporation into large-scale integration processes at sub-100 nm channel length. The reliability study includes a discussion of the evolution of current with time during a constant voltage stress, deduction of Weibull slopes, voltage acceleration and an estimate of the 10-year maximum operating voltage for devices fabricated with these layers. Finally, the change in Weibull slope at increased current step magnitude for constant voltage stress is used to observe the change in trap generation rate during a CVS until breakdown.
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