Large Scale Integration Circuits Research Articles

Design of Flash analog-to-digital converter based on MoS2 FET

In this paper, we leverage the advantages of MoS2 FETs to design a 4-bit Flash ADC that achieves a reduced active area and dynamic power. The proposed ADC employs a threshold inverter quantization (TIQ) technique to eliminate static power dissipation. A SPICE-compatible charge-based model for MoS2 FETs is used to simulate the proposed ADC. The high ON/OFF current ratio and nanoscale size of MoS2 FETs contribute to a smaller ADC active area and lower dynamic power compared to other technologies. Simulation results indicate a differential nonlinearity (DNL) of [−0.18, 0.12]LSB and an integral nonlinearity (INL) of [−0.32, 0.24]LSB meeting the requirements for 4-bit resolution at a 2 V operating voltage. While the FFT spectrum analysis reveals a signal-to-noise ratio (SNR) of 29.37 dB, the effective resolution bandwidth (ERBW) of 2.2 GHz is obtained, highlighting the ADC’s performance in high-speed applications. Additionally, the low ADC active area of 3000 μm2 makes it suitable for very large-scale integration (VLSI) circuits. The proposed method is sensitive to variations in process, temperature, and power supply voltage, and their effects on ADC performance are also examined.

A study of advances in machine learning-based electronic design automation

Abstract. The electronic design automation (EDA) is a convenient tool for designing integrated circuits (IC), which is employed extensively both in academic and engineering. The design of integrated circuits is conducted in accordance with a defined design flow, commonly referred to as the chip design flow, which can be divided into two distinct parts, the front-end design and the back-end design. Following a long period of evolution, the chip design flow of EDA has been gradually improved. Besides, it achieved some accomplishments during this period. However, with the growing demand of ICs, especially Very Large-Scale Integration Circuit (VLSI), the existing EDA is not adequate for the requirement. In addition, the EDA technology has been so developed that it is relatively less flexible. In this context, concerns about the future of EDA have recently emerged. In response to this challenge, research has mentioned that machine learning methods (ML methods) can improve the functionality of EDA. The ML method covers most of steps of EDAs design flow, especially back-end design. The machine learning-based electronic design automation is still in its infancy, which is presented with a multitude of challenges. Therefore, the paper explores the development of EDA by reviewing and organizing the related literature, and summarizes the application of ML methods in EDA, thereby providing the future development trend of ML-based EDA.

AI-Augmented Fault Detection and Diagnosis in VLSI Circuits: A Step toward Intelligent Chip Design

Fault detection and diagnosis are critical challenges in Very Large Scale Integration (VLSI) circuits, where even minor defects can cause significant performance degradation or system failure. Traditional fault detection methods often struggle with scalability and real-time analysis as circuits grow increasingly complex. This paper proposes an AI-augmented framework that leverages machine learning algorithms and neural networks to enhance the fault detection process in VLSI circuits. The proposed model not only identifies and classifies faults with high accuracy but also provides root-cause diagnostics, significantly reducing testing time and maintenance costs. Simulation results demonstrate the effectiveness of the AI-based approach in comparison with conventional techniques, showcasing improved fault coverage, faster detection, and scalability for modern chip designs. This study serves as a step toward the integration of intelligent diagnostics into chip manufacturing, paving the way for more robust and self-healing electronic systems.

Structural designs and synthesis of co-polycarbonates with cyclohexyl and fluorene structures: Low-dielectric constant, high solubility, and superior mechanical properties

The rapid developments of high-speed communication and large-scale integrated circuits have accelerated the research for insulating dielectric materials with low dielectric constant, low dielectric loss, and good mechanical properties. In this study, a series of polycarbonate resins containing cyclohexyl and fluorene structures are synthesized by melt transesterification, which is low dielectric, highly thermally resistant, and soluble. The effects of fluorene structure contents on the properties of a co-polycarbonate resin were studied systematically. The results showed that the non-polar fluorene group could reduce the molecular polarization of co-polycarbonate, resulting in low permittivity of co-polycarbonate are 2.41–2.71@1 MHz. In addition, the resin has excellent solubility and can be dissolved in NMP, CH2Cl2, THF, and other solvents at room temperature. Furthermore, the co-polycarbonate resins also exhibit superior heat resistance with glass transition temperature (Tg) of 160.6–173.1 °C as well as admirable mechanical properties with a tensile strength of 50.54–70.72 MPa. This makes it a promising candidate for high-speed communications and large-scale integrated circuits.

Performance analysis of meta-heuristic optimization techniques for multi-objective VLSI circuit partitioning

Abstract The efficiency of various stages of physical design in the Very Large Scale Integration (VLSI) circuit can be enhanced by using multi-objective optimization techniques. The circuit is partitioned into a set of modules at the beginning of the physical design phase. This step is known as circuit partitioning. All subsequent physical design stages, like floor planning, placement, pin configuration, and routing etc, are influenced by the outcome of the circuit partitioning method being used. The efficiency of the partitioning method controls the quality of ultimate architecture. The efficiency achieved by the final product may be decreased by incorrect partitioning. This study compares the effectiveness of four Meta-heuristic optimization methods include the Genetic Algorithm (GA), Satin Bowered Bird (SBO), Particle Swarm Optimization (PSO), Simulated Annealing (SA) — in terms of number of net cut, duration of sleeping mode, and efficiency in power consumption for addressing the VLSI circuit partitioning problem. This experiment achieves K-way partitioning of the circuit that minimizes net cuts as well as maximizes sleep duration simultaneously, by evaluating optimization function. Solutions developed using GA, SBO and PSO consistently surpass those acquired using SA with respect to quality of optimal solution. The average optimum net cut and sleep duration achieved by this experiment are 10.7 and 9.9 in GA ; 11.5 and 12.3 in SBO, 11.80 and 9.10 in PSO; and 16.8 and 6.7 in SA based method respectively. This research resulted in a considerable reduction in power consumption, with the system’s average power efficiency achieved by 21.6%, 26.84%, 19.85%, and 14.62%, respectively, in GA, SBO , PSO, and SA based optimizations. The experimental results are compared with a recent publication and proposed GA, SBO, and PSO based methods achieve 18.75%, 4.17%, and 1.04% improvement in terms of average net cut respectively. The proposed GA, SBO, PSO and SA based methods also achieve 44.90%, 51.30%, 40.05%, and 18.60% improvement in terms of average power efficiency.

High-performance single-crystalline In2O3 field effect transistor toward three-dimensional large-scale integration circuits

Formation of a single crystalline oxide semiconductor on an insulating film as a channel material capable of three-dimensional (3D) stacking would enable 3D very-large-scale integration circuits. This study presents a technique for forming single-crystalline In2O3 having no grain boundaries in a channel formation region on an insulating film using the (001) plane of c-axis-aligned crystalline indium gallium zinc oxide as a seed. Vertical field-effect transistors using the single-crystalline In2O3 had an off-state current of 10−21 A μm−1 and electrical characteristics were improved compared with those using non-single-crystalline In2O3: the subthreshold slope was improved from 95.7 to 86.7 mV dec.−1, the threshold voltage showing normally-off characteristics (0.10 V) was obtained, the threshold voltage standard deviation was improved from 0.11 to 0.05 V, the on-state current was improved from 22.5 to 28.8 μA, and a 17-digit on/off ratio was obtained at 27 °C.

Design and analysis of low power sense amplifier for static random access memory

<p>Today’s era is a digital world where each and every section of the society is experiencing and encountering with semiconductor chips. In very large-scale integration (VLSI) circuits the design of static random-access memory (SRAM) plays a crucial role in ensuring both low-power consumption and high-speed performance. The sense amplifiers (SA) are integral parts for information accessing storage in SRAM IC design. This paper introduces a dual voltage latch sense amplifier (DVLSA) for SRAM integrated circuits (IC). The comparative analyses of various SA are studied and then design a low-power SA through the implementation of energy-efficient technique. Further, we have elucidated the causes of delay and power dissipation in different SA with useful solutions and performance evaluation is conducted by comparing the proposed design with existing SA reported in the literature. The performance parameters such as power 1.604 uw, energy 470.50 fJ, delay 80.04 ps, and current 5.406 are scrutinized to assess the efficiency of the designs. The cell outcomes have been validated with cadence tool on 180 nm technology and operate at 1.8 V. The proposed design, namely, DVLSA demonstrates minimal energy consumption and low power dissipation, making it a promising advancement in SRAM IC technology.</p>

Site-Selective Synthesis of Bilayer Graphene on Cu Substrates Using Titanium as a Carbon Diffusion Barrier.

Chemical vapor deposition (CVD) is a widely used method for graphene synthesis, but it struggles to produce large-area uniform bilayer graphene (BLG). This study introduces a novel approach to meet the demands of large-scale integrated circuit applications, challenging the conventional reliance on uniform BLG over extensive areas. We developed a unique method involving the direct growth of bilayer graphene arrays (BLGA) on Cu foil substrates using patterned titanium (Ti) as a diffusion barrier. The use of the Ti layer can effectively control carbon atom diffusion through the Cu foil without altering the growth conditions or compromising the graphene quality, thereby showcasing its versatility. The approach allows for targeted BLG growth and achieved a yield of 100% for a 10 × 10 BLG units array. Then a 10 × 10 BLG memristor array was fabricated, and a yield of 96% was achieved. The performances of these devices show good uniformity, evidenced by the set voltages concentrated around 4 V, and a high resistance state (HRS) to low resistance state (LRS) ratio predominantly around 107, reflecting the spatial uniformity of the prepared BLGA. This study provides insight into the BLG growth mechanism and opens new possibilities for BLG-based electronics.

Improving Predective Accuracy In Vlsi Circut Design With Synthetic Data Generation

An essential component of promoting innovation and dependability in contemporary electronic systems is the pursuit of improved prediction accuracy in the field of very large-scale integration (VLSI) circuit design. However, the problem of inadequate data frequently arises in the traditional design routes, making it difficult to achieve the appropriate level of precision. To improve the accuracy of future machine learning models in activities like performance evaluation, design, and testing—where training data is typically known to be very limited— this work explores the use of diffusion models to generate false data for electrical circuits. To support our suggested diffusion model, we conduct simulations in the HSPICE design environment using 22nm CMOS technology nodes to get real-world training data that is typical of the situation. Our findings show that data generated artificially via diffusion model closely resembles genuine data. We confirm the accuracy of the produced data and show that data augmentation is definitely useful for digital circuit VLSI design prediction analysis.

Morphology Control and Mechanism of Different Bath Systems in Cu/SiCw Composite Electroplating.

With the rapid development of electronic technology and large-scale integrated circuit devices, it is very important to develop thermal management materials with high thermal conductivity. Silicon carbide whisker-reinforced copper matrix (Cu/SiCw) composites are considered to be one of the best candidates for future electronic device radiators. However, at present, most of these materials are produced by high-temperature and high-pressure processes, which are expensive and prone to interfacial reactions. To explore the plating solution system suitable for SiCw and Cu composite electroplating, we tried two different Cu-based plating solutions, namely a Systek UVF 100 plating solution of the copper sulfate (CuSO4) system and a Through Silicon Via (TSV) plating solution of the copper methanesulfonate (Cu(CH3SO3)2) system. In this paper, Cu/SiCw composites were prepared by composite electrodeposition. The morphology of the coating under two different plating liquid systems was compared, and the mechanism of formation of the different morphologies was analyzed. The results show that when the concentration of SiCw in the bath is 1.2 g/L, the surface of the Cu/SiCw composite coating prepared by the CuSO4 bath has more whiskers with irregular distribution and the coating is very smooth, but there are pores at the junction of the whiskers and Cu. There are a large number of irregularly distributed whiskers on the surface of the Cu/SiCw composite coating prepared with the copper methanesulfonate (Cu(CH3SO3)2) system. The surface of the composite is flat, and Cu grows along the whisker structure. The whisker and Cu form a good combination, and there is no pore in the cross-section of the coating. The observation at the cross-section also reveals some characteristics of the toughening mechanism of SiCw, including crack deflection, bridging and whisker pull-out. The existence of these mechanisms indicates that SiCw plays a toughening role in the composites. A suitable plating solution system was selected for the preparation of high-performance Cu/SiCw thermal management materials with the composite electrodeposition process.

Ultrahigh extinction ratio and a low power silicon thermo-optic switch.

The silicon thermo-optic switch (TOS) is one of the most fundamental and crucial blocks in large-scale silicon photonic integrated circuits (PICs). An energy-efficient silicon TOS with ultrahigh extinction ratio can effectively mitigate cross talk and reduce power consumption in optical systems. In this Letter, we demonstrate a silicon TOS based on cascading Mach-Zehnder interferometers (MZIs) with spiral thermo-optic phase shifters. The experimental results show that an ultrahigh extinction ratio of 58.8 dB is obtained, and the switching power consumption is as low as 2.32 mW/π without silicon air trench. The rise time and fall time of the silicon TOS are about 10.8 and 11.2 µs, respectively. Particularly, the figure of merit (FOM) has been improved compared with previously reported silicon TOS. The proposed silicon TOS may find potential applications in optical switch arrays, on-chip optical delay lines, etc.

Exploring the significance and applications of Field Programmable Gate Arrays in modern integrated circuits

In recent years, the rapid advancement of electronic technology and large-scale integrated circuit technology has led to increased integration of integrated circuits and expanding system scales on integrated motherboards. This evolution presents new challenges and demands in system design. Field Programmable Gate Arrays (FPGAs), a vital VLSI technology, have found extensive applications in communication, image processing, computers, and other domains, becoming a pivotal component of contemporary electronic systems. This paper aims to enhance the understanding of FPGAs by first delving into their theoretical foundations, followed by an overview of their general structural elements and a historical perspective on FPGA development. Additionally, this analyse and summarize relevant literature in the third section, focusing on the three primary application areas of FPGAs, elucidating their research processes and findings. Finally, the fourth section offers insights into the future directions of FPGA development, grounded in the current context. By acquainting readers with FPGAs essential attributes and its multifaceted applications, this paper underscores the pivotal role of FPGAs in the landscape of modern integrated circuits.

MICRO-AND NANOCIRCUITS WITH PROGRAMMABLE STRUCTURES

In this work, structural programming does not mean the creation of algorithms for processing multi-argument functions by changing the operating pro- grams, as implemented by the microprocessor, but rather technological changes in the large-scale integrated circuits (LSIC) configurations in such a way as to synthesize logical functions at the structural-logical level. During the automated design and manufacture of programmable LSIC (FPGA or CPLD), the same technological cycle is used as for specialized circuits. Obviously, such LSICs are universal for technologists. However, programming of individual LSICs that implement given functions is performed by the user. Thus, the main advantage of universal (FPGA, CPLD) programmable LSIC over specialized ones is low cost, which is fundamentally important for small-scale production. Currently, the increase in the universality of LSIC is always accompanied by a decrease in their special application. Such inconsistency is revealed in the initial stages of automated hierarchical design. Universal micro- and nanocircuits with programmable structures are used to increase the efficiency of CAD. One of the advantages of programmable logic integrated circuits (PLCs) over LSIC is a short manufacturing time with predetermined charac- teristics. At the same time, a standard micro- or nanocircuit is taken and its parameters are directly changed by applying special signals to certain in- puts or connecting the outputs accordingly. This advantage determines the main purpose of such FPGAs - the replacement of groups of logic ICs of medium and large degrees of integration. Multiplexers can be used as simple FPGAs. The article introduces effective methods of multivariate pro- gramming of multiplexer MNPS for reproduction of Boolean and majority logic functions. The obtained results can be used for reprogramming multi- plexer functional blocks of programmable integrated circuits. Comparative modeling of logical MNPS was performed on modern CAD systems, which proved the adequacy of their functioning, advantages of frequency and disadvantages of temperature characteristics of nanomultiplexer circuits.

High-speed and large-scale intrinsically stretchable integrated circuits.

Intrinsically stretchable electronics with skin-like mechanical properties have been identified as a promising platform for emerging applications ranging from continuous physiological monitoring to real-time analysis of health conditions, to closed-loop delivery of autonomous medical treatment1-7. However, current technologies could only reach electrical performance at amorphous-silicon level (that is, charge-carrier mobility of about 1 cm2 V-1 s-1), low integration scale (for example, 54 transistors per circuit) and limited functionalities8-11. Here we report high-density, intrinsically stretchable transistors and integrated circuits with high driving ability, high operation speed and large-scale integration. They were enabled by a combination of innovations in materials, fabrication process design, device engineering and circuit design. Our intrinsically stretchable transistors exhibit an average field-effect mobility of more than 20 cm2 V-1 s-1 under 100% strain, a device density of 100,000 transistors per cm2, including interconnects and a high drive current of around 2 μA μm-1 at a supply voltage of 5 V. Notably, these achieved parameters are on par with state-of-the-art flexible transistors based on metal-oxide, carbon nanotube and polycrystalline silicon materials on plastic substrates12-14. Furthermore, we realize a large-scale integrated circuit with more than 1,000 transistors and a stage-switching frequency greater than 1 MHz, for the first time, to our knowledge, in intrinsically stretchable electronics. Moreover, we demonstrate a high-throughput braille recognition system that surpasses human skin sensing ability, enabled by an active-matrix tactile sensor array with a record-high density of 2,500 units per cm2, and a light-emitting diode display with a high refreshing speed of 60 Hz and excellent mechanical robustness. The above advancements in device performance have substantially enhanced the abilities of skin-like electronics.

An efficient algorithm for estimating gate-level power consumption in large-scale integrated circuits

Estimating power dissipation in Very Large Scale Integrated (VLSI) circuits, particularly large-scale sequential circuits, is a significant challenge in Electronic Design Automation (EDA). Benchmarked against PrimeTime PX, the proposed algorithm proficiently analyzes large-scale combinational and sequential circuits. This research begins with a power analysis algorithm for combinational circuits, focusing on signal probability (SP) and transition count (TC). It then extends to sequential circuits, introducing methodologies for loopback issues and a validity-checking mechanism for spatial dependency topology. Developed on the OpenTimer open-source framework using the SMIC 40-nm process library, the algorithm was validated on academic and industrial datasets. Experimental evaluations show that our algorithm outperforms in terms of speed and accuracy. For power analysis with vector annotations, it achieves an average error within 0.16% in power testing of large-scale timing circuits. It also performs gate-level vectorless power analysis on complex topology and large-scale integrated circuits, demonstrating computational robustness.

Low-temperature process design for inversion mode n-channel thin-film-transistor on polycrystalline Ge formed by solid-phase crystallization

We fabricated an inversion mode n-channel thin-film-transistor (TFT) on polycrystalline (poly-) Ge at low temperatures for monolithic three-dimensional large-scale IC (3D-LSI) and flexible electronics applications. Based on our previously reported solid-phase crystallization (SPC) method, we designed an n-channel TFT fabrication process with phosphorous ion implantation to provide the source/drain (S/D). We succeeded in fabricating an n-channel TFT with typical electrical characteristics on poly-Ge and confirmed its operation mode to be inversion mode. However, the fabrication process included a high temperature (500 °C) step for S/D activation. To reduce the process temperature, we used a metal-induced dopant activation method and successfully reduced the activation temperature to 360 °C. This combination is expected to pave the way for high-performance 3D-LSI and flexible electronic devices based on SPC-Ge.

IMPACT OF SUPPLY VOLTAGE ON SRAM CELL POWER DISSIPATION UNDER DIFFERENT TOPOLOGIES

The high storage density and quick access times of Static Random Access Memory (SRAM) make it a critical component of many Very Large Scale Integration circuits. However, device scaling in today's technology leads to an increase in dynamic power and a decrease in noise margin, posing significant challenges to memory circuit design for the next generation of devices. In addition, sub-threshold leakage is also a concern. In recent years, the increasing demand for notebooks, laptops, IC memory cards, and mobile communication devices has driven the development of low-power, low-voltage memory circuits. Static Random Access Memoryis widely used as on-chip and off-chip memory for portable applications because they are easy to use and have minimal standby leakage. Since 60% to 70% of the chip memory is used, SRAM optimization is the focus of research. The SRAM cell's architecture and performance have been studied using various technologies to minimize power dissipation while maintaining stability. Based on the power dissipation, including static and dynamic power dissipation, and Static Noise Margin (SNM), the SRAM cell performance is compared with different topologies. The SNM fluctuation is considered along with the variation of supply voltage.

Research on Methods for Very Large Scale Integration Track Assignment Routing

Routing is a crucial stage in the physical design of Very Large Scale Integration (VLSI) circuits, comprising three phases: global routing, track assignment routing, and detailed routing. With the development of VLSI circuits, scholars have proposed various track assignment routing algorithms. However, improving the efficiency of track assignment routing and optimizing conflicting design rules have become bottlenecks in track assignment routing problems. This study addresses these bottlenecks by utilizing single-level horizontal and vertical Steiner trees to extract routability information of local wire nets, resolving the adaptation issue between global routing and detailed routing. The proposed algorithm enhances routability information by an average of 16.07% across ten benchmark circuits. Additionally, a Generative Neural Network model based on Conditional Variational Autoencoder (CVAE) is employed to improve the efficiency of track assignment routing, yielding significant simulation results. Furthermore, a negotiation-based tear-and-reassign approach is utilized to address track congestion issues, resulting in an average optimization of 26.03% in overlap cost, with a tradeoff of sacrificing 6.67% of wirelength on average.

Estimating R, L and C in Arithmetic Circuits using ML

In Very Large Scale Integration (VLSI) circuits, the estimation techniques for resistors (R), inductors (L), and capacitors (C) heavily rely on segmented circuit analysis, which involves usage of complex mathematical simplification models. These methods have been conventionally applied to estimate the behavior of circuits, but when faced with systems featuring unique circuit architectures, they often encounter inaccuracies and limitations. The significance of adders as fundamental building blocks in intricate circuit design cannot be overstated. In such complex circuits, various parameters, including parasitic resistances, inductances, and capacitances, engage an indispensable effort in the analysis of delays and performance. However, the conventional estimation methods fail to address the complexities of these systems and the impacts of parasitics accurately. To overcome these challenges, this paper proposes a novel approach that harnesses the potential of machine learning algorithms. By integrating machine learning into the estimation process, the research aims to achieve specific and precise analysis methods that can cater to the needs of modern VLSI circuits. The proposed methodology involves collecting a comprehensive dataset using different adder circuits. From each individual adder circuit layout, the relevant information on resistors, capacitors, and inductors is carefully extracted and compiled. This dataset serves as the foundation for training the machine learning models. Three standard machine learning models are employed in this study: adaboost, Tree, and k-Nearest Neighbors (kNN). Their task is to predict the values of resistors, inductors, and capacitors based on the input data from the adder circuits. Among these models, adaboost proves to be the most effective, exhibiting superior performance by achieving a reduced root mean square error of about 0.008. When compared to the Tree and kNN models, adaboost stands out as the optimal choice for accurately estimating the R values in VLSI circuits.

High-Q adiabatic micro-resonators on a wafer-scale ion-sliced 4H-silicon carbide-on-insulator platform.

A 4H-silicon carbide-on-insulator (4H-SiCOI) has emerged as a prominent material contender for integrated photonics owing to its outstanding material properties such as CMOS compatibility, high refractive index, and high second- and third-order nonlinearities. Although various micro-resonators have been realized on the 4H-SiCOI platform, enabling numerous applications including frequency conversion and electro-optical modulators, they may suffer from a challenge associated with spatial mode interactions, primarily due to the widespread use of multimode waveguides. We study the suppression of spatial mode interaction with Euler bends, and demonstrate micro-resonators with improved Q values above 1 × 105 on ion-sliced 4H-SiCOI platform with a SiC thickness nonuniformity less than 1%. The spatial-mode-interaction-free micro-resonators reported on the CMOS-compatible wafer-scale 4H-SiCOI platform would constitute an important ingredient for the envisaged large-scale integrated nonlinear photonic circuits.