Large Scale Integrated Circuit Fabrication Research Articles

High Accuracy Correction of Critical Dimension Errors Appearing in Large Scale Integrated Circuits Fabrication Processes: Pattern-Based Model

The pattern density model has been used for correcting critical dimension (CD) errors appearing in LSI fabrication processes. However, this method has an inherent uncertainty in the figure position and a correction error caused by this uncertainty. In this paper, we introduce a pattern-based model for discussing CD errors in order to avoid this uncertainty. Based on the pattern-based model, a new nonlinear equation for correction is derived, and a formula for obtaining a high-accuracy numerical solution for the correction equation is also derived. The correction accuracy of the solution is evaluated with several approximate solutions by both analytical and numerical methods under the condition that (1) the point spread function g(x) of the position shift of a point on a figure edge is the Gaussian function, and (2) a one-dimensional cross section of lines and spaces is used for evaluation. The proposed method can provide a high-accuracy correction both in the case in which the interaction distance σ≫figure size and also when σ≪figure size. Furthermore, even in the case in which σ is comparable with figure size, the method provides higher-accuracy corrections than other methods. For example, when σ is 10 nm, the figure size is 20 nm, and the maximum deviation γd(=2γd*) from the designed size is 20 nm, our correction method supresses the dimensional error of lines and speces pattern less than 0.9 nm. These results suggest that the method proposed in this paper has a wide range of applications for future LSI fabrication.

High-accuracy correction of critical dimension errors taking sequence of large-scale integrated circuits fabrication processes into account

We previously proposed a new method to correct critical dimension (CD) errors appearing in large-scale integrated circuit (LSI) fabrication processes, such as long range loading effect, local flare, and micro loading effect. The method provides high accuracy correction dimensions when using the pattern modulation method (method correcting CD errors by controlling figure sizes of LSI patterns). Now the case that several processes cause CD errors when a layer of an LSI pattern is fabricated on a wafer is discussed. These CD errors are corrected by generalizing the method proposed previously and taking the sequence of processes into account. It is shown from numerical calculation that the method can suppress the CD error to less than 0.01 nm with three iterations, under the condition that the maximum CD errors by micro loading effect and flare are 10 nm and 20 nm, respectively. It is strongly suggested that our methods will provide the necessary CD accuracies in the future.

A combination of characteristics and Monte Carlo methods for etch profile simulation

A method of characteristics is applied with Monte Carlo simulation for the first time in the ion-assisted plasma etch profile calculation. The characteristic equations of etch profile evolution are derived. The Monte Carlo simulations of ions and neutrals transport are discussed. A five-point, non-uniform spatial smoothing scheme, and an adaptive spatial and temporal step size algorithm are used to solve the characteristic equations coupled to a Monte Carlo technique. The numerical results show that a successful computer model based on a rigorous mathematical method and simulation is achieved for the study of etch profile evolution in the very large scale integrated circuit fabrication.

Modeling of the Kinetics of Dopant Precipitation in Silicon

In heavily doped silicon, dopant aggregation leads to a reduction in the electrically active concentration. For thermal cycles typical of very large scale integrated circuit fabrication, the kinetics of this precipitation process can play a critical role in determining the active doping levels and thus device electrical characteristics. In this work, we develop a general kinetic precipitation model which explicitly considers the time evolution of the precipitate size density, and is thus able to account for a broad range of behavior. We compare our model to previously published experimental data for arsenic and phosphorus activation/deactivation in silicon over a wide temperature range (300 to 800°C), and find that it can account accurately for the experimental observations, including reverse annealing following a temperature step.

Application of x-ray lithography with a single-layer resist process to subquartermicron large scale integrated circuit fabrication

The applicability of synchrotron radiation x-ray lithography to future ultralarge scale integrated circuit fabrication processes is demonstrated by the test fabrication of subquartermicron bipolar- complementary metaloxide semiconductor devices (SRAM, gate arrays, and several test element groups) with a total size of two-million transistors. Synchrotron radiation lithography is used at four critical levels: gate poly, first metal, via hole, and second metal. Both negative and positive chemically amplified resists are used with a single-layer resist system to simplify the resist process. An overview of the lithography process is presented with emphasis on patterning and overlay performance.

Some applications of microanalytical techniques in very large scale integrated circuits fabrication

The trend in technology development for the fabrication of very large scale integrated circuits (IC’s) continues in the direction of increased density of components with smaller dimensions. Devices with submicron dimension are currently either in manufacture or in development stage. The scaling down of device dimensions, both laterally and in depth, has resulted in new challenges and developments in material and process technologies. The successful implementation of these technologies in the fabrication of reliable devices is critically dependent on the proper understanding of the material properties, the processes, and their interactions. The need for analytical tools with high spatial resolution (∼nm range), depth resolution, and ultralow detectable limits (≪parts per 109) continues. The characterization efforts have been aided by the emergence and maturing of a variety of sophisticated analytical techniques aimed at physical, chemical, and electrical characterization. The physical and chemical methods include various microscopy techniques, surface, interface, and bulk compositional analysis, and trace chemical analysis tools each with its own strengths and weaknesses. Usually multiple techniques are necessary and are used in a synergistic manner for a comprehensive analysis. The application of a particular technique varies based on the emphasis on material, process development, process monitoring, yield enhancement, or device failure analysis. Typical examples of application of various microanalytical techniques to process development for IC fabrication are presented and some of the current challenges facing analysts are identified.

High temperature stability of plasma-enhanced chemically vapour deposited titanium silicide due to two-step rapid thermal annealing

The high temperature stability of plasma-enhanced chemically vapour deposited titanium silicide (TiSi x ) annealed at 1000°C is studied. A multilayer structure consisting of Si(1000 Å)/TiSi x (1200 Å)/Si(700 Å) is deposited successively over thermal oxide on a silicon substrate. When one-step rapid thermal annealing is performed at 1000 °C, a rough TiSi x Si interface forms and an increase in sheet resistance occurs. However, a stable interface and sheet resistance can be attained using a two-step rapid thermal sequence consisting of a 700°C pre-anneal and 1000°C post-anneal owing to the fact that stoichiometric TiSi x possessing an even TiSi x Si interface is formed with this pre-anneal. Pre-anneals at 600 and 800°C result in an inhomogeneous interface when followed by the post-anneal at 1000°C. Two-step annealing with a 700°C pre-anneal is a promising process technology for very large scale integrated circuit fabrication.

AlGaAs/GaAs heterojunction bipolar transistors fabricated using a self-aligned dual-lift-off process

This paper describes a self-aligned heterojunction-bipolar-transistor (HBT) process based on a simple dual-lift-off method. Transistors with emitter width down to 1.2 µm and base doping up to 1 × 1020/cm3have been fabricated. Extrapolated current gain cutoff frequency f t of 55 GHz and maximum frequency of oscillation f_{\max} of 105 GHz have been obtained. Current-mode-logic (CML) ring oscillators with propagation delays as low as 14.2 ps have been demonstrated. These are record performance results for bipolar transistors. The dual-lift-off process is promising for both millimeter-wave devices and large-scale integrated circuit fabrication.

Instrument measuring temperature dependence of minority-carrier lifetime without contact

An instrument measuring the temperature dependence of minority-carrier lifetimes without contacts is described. The temperature range is 100 to 420 K, and the shortest decay time observed is about 2 μs. The instrument utilizes the photo decay of microwave power reflected from the sample, therefore, it is a contactless method. As an example, the instrument was applied to high-quality silicon crystals used in very large scale integrated circuit fabrication. The measured temperature dependence could be explained by the Shockley–Read–Hall theory by assuming a level for the recombination centers at 0.18 eV from the valence band.

Planarizing of phosphosilicate glass films on patterned silicon wafers

Patterned silicon wafers covered with both flowed and nonflowed phosphosilicate glass films have been planarized by argon ion‐beam etching. At the optimum planarizing angle of 50°, the nonflowed PSG surface, with 1 μm high topography, is transformed to a flat surface with maximum deviations from planarity of <500 A. The technique should alleviate resolution, linewidth control, and metallization coverage problems in very large scale integrated circuit fabrication.

The Structure and Properties of MoSi2 Thin Film in Mos Process

Recently, the use of refractory metal silicides as low resistivity, high temperature and high oxidation resistance gate materials in large scale integrated circuits (LSI) has become an important approach in advanced MOS process development (1). This research is a systematic study on the structure and properties of molybdenum silicide thin film and its applicability to high performance LSI fabrication.

Implementation of linear programming with a digital stochastic computer

The problem of online computation of linear-programming problems with digital-stochastic-computing structures is considered. Such techniques are shown to provide very economical and fast online computations. The simple logic-circuits used for the realisation of the stochastic operators are ideally suited for large-scale integrated-circuit fabrication. Experimental results are presented for the stochastic computation of linear programming with an algorithm based on steepest-descent techniques.