High-accuracy correction of critical dimension errors taking sequence of large-scale integrated circuits fabrication processes into account

Abstract

We previously proposed a new method to correct critical dimension (CD) errors appearing in large-scale integrated circuit (LSI) fabrication processes, such as long range loading effect, local flare, and micro loading effect. The method provides high accuracy correction dimensions when using the pattern modulation method (method correcting CD errors by controlling figure sizes of LSI patterns). Now the case that several processes cause CD errors when a layer of an LSI pattern is fabricated on a wafer is discussed. These CD errors are corrected by generalizing the method proposed previously and taking the sequence of processes into account. It is shown from numerical calculation that the method can suppress the CD error to less than 0.01 nm with three iterations, under the condition that the maximum CD errors by micro loading effect and flare are 10 nm and 20 nm, respectively. It is strongly suggested that our methods will provide the necessary CD accuracies in the future.