High Accuracy Correction of Critical Dimension Errors Appearing in Large Scale Integrated Circuits Fabrication Processes: Pattern-Based Model

Abstract

The pattern density model has been used for correcting critical dimension (CD) errors appearing in LSI fabrication processes. However, this method has an inherent uncertainty in the figure position and a correction error caused by this uncertainty. In this paper, we introduce a pattern-based model for discussing CD errors in order to avoid this uncertainty. Based on the pattern-based model, a new nonlinear equation for correction is derived, and a formula for obtaining a high-accuracy numerical solution for the correction equation is also derived. The correction accuracy of the solution is evaluated with several approximate solutions by both analytical and numerical methods under the condition that (1) the point spread function g(x) of the position shift of a point on a figure edge is the Gaussian function, and (2) a one-dimensional cross section of lines and spaces is used for evaluation. The proposed method can provide a high-accuracy correction both in the case in which the interaction distance σ≫figure size and also when σ≪figure size. Furthermore, even in the case in which σ is comparable with figure size, the method provides higher-accuracy corrections than other methods. For example, when σ is 10 nm, the figure size is 20 nm, and the maximum deviation γd(=2γd*) from the designed size is 20 nm, our correction method supresses the dimensional error of lines and speces pattern less than 0.9 nm. These results suggest that the method proposed in this paper has a wide range of applications for future LSI fabrication.