Large Scale Integration Circuits Research Articles

Ultrahigh extinction ratio and a low power silicon thermo-optic switch.

The silicon thermo-optic switch (TOS) is one of the most fundamental and crucial blocks in large-scale silicon photonic integrated circuits (PICs). An energy-efficient silicon TOS with ultrahigh extinction ratio can effectively mitigate cross talk and reduce power consumption in optical systems. In this Letter, we demonstrate a silicon TOS based on cascading Mach-Zehnder interferometers (MZIs) with spiral thermo-optic phase shifters. The experimental results show that an ultrahigh extinction ratio of 58.8 dB is obtained, and the switching power consumption is as low as 2.32 mW/π without silicon air trench. The rise time and fall time of the silicon TOS are about 10.8 and 11.2 µs, respectively. Particularly, the figure of merit (FOM) has been improved compared with previously reported silicon TOS. The proposed silicon TOS may find potential applications in optical switch arrays, on-chip optical delay lines, etc.

Exploring the significance and applications of Field Programmable Gate Arrays in modern integrated circuits

In recent years, the rapid advancement of electronic technology and large-scale integrated circuit technology has led to increased integration of integrated circuits and expanding system scales on integrated motherboards. This evolution presents new challenges and demands in system design. Field Programmable Gate Arrays (FPGAs), a vital VLSI technology, have found extensive applications in communication, image processing, computers, and other domains, becoming a pivotal component of contemporary electronic systems. This paper aims to enhance the understanding of FPGAs by first delving into their theoretical foundations, followed by an overview of their general structural elements and a historical perspective on FPGA development. Additionally, this analyse and summarize relevant literature in the third section, focusing on the three primary application areas of FPGAs, elucidating their research processes and findings. Finally, the fourth section offers insights into the future directions of FPGA development, grounded in the current context. By acquainting readers with FPGAs essential attributes and its multifaceted applications, this paper underscores the pivotal role of FPGAs in the landscape of modern integrated circuits.

MICRO-AND NANOCIRCUITS WITH PROGRAMMABLE STRUCTURES

In this work, structural programming does not mean the creation of algorithms for processing multi-argument functions by changing the operating pro- grams, as implemented by the microprocessor, but rather technological changes in the large-scale integrated circuits (LSIC) configurations in such a way as to synthesize logical functions at the structural-logical level. During the automated design and manufacture of programmable LSIC (FPGA or CPLD), the same technological cycle is used as for specialized circuits. Obviously, such LSICs are universal for technologists. However, programming of individual LSICs that implement given functions is performed by the user. Thus, the main advantage of universal (FPGA, CPLD) programmable LSIC over specialized ones is low cost, which is fundamentally important for small-scale production. Currently, the increase in the universality of LSIC is always accompanied by a decrease in their special application. Such inconsistency is revealed in the initial stages of automated hierarchical design. Universal micro- and nanocircuits with programmable structures are used to increase the efficiency of CAD. One of the advantages of programmable logic integrated circuits (PLCs) over LSIC is a short manufacturing time with predetermined charac- teristics. At the same time, a standard micro- or nanocircuit is taken and its parameters are directly changed by applying special signals to certain in- puts or connecting the outputs accordingly. This advantage determines the main purpose of such FPGAs - the replacement of groups of logic ICs of medium and large degrees of integration. Multiplexers can be used as simple FPGAs. The article introduces effective methods of multivariate pro- gramming of multiplexer MNPS for reproduction of Boolean and majority logic functions. The obtained results can be used for reprogramming multi- plexer functional blocks of programmable integrated circuits. Comparative modeling of logical MNPS was performed on modern CAD systems, which proved the adequacy of their functioning, advantages of frequency and disadvantages of temperature characteristics of nanomultiplexer circuits.

High-speed and large-scale intrinsically stretchable integrated circuits.

Intrinsically stretchable electronics with skin-like mechanical properties have been identified as a promising platform for emerging applications ranging from continuous physiological monitoring to real-time analysis of health conditions, to closed-loop delivery of autonomous medical treatment1-7. However, current technologies could only reach electrical performance at amorphous-silicon level (that is, charge-carrier mobility of about 1 cm2 V-1 s-1), low integration scale (for example, 54 transistors per circuit) and limited functionalities8-11. Here we report high-density, intrinsically stretchable transistors and integrated circuits with high driving ability, high operation speed and large-scale integration. They were enabled by a combination of innovations in materials, fabrication process design, device engineering and circuit design. Our intrinsically stretchable transistors exhibit an average field-effect mobility of more than 20 cm2 V-1 s-1 under 100% strain, a device density of 100,000 transistors per cm2, including interconnects and a high drive current of around 2 μA μm-1 at a supply voltage of 5 V. Notably, these achieved parameters are on par with state-of-the-art flexible transistors based on metal-oxide, carbon nanotube and polycrystalline silicon materials on plastic substrates12-14. Furthermore, we realize a large-scale integrated circuit with more than 1,000 transistors and a stage-switching frequency greater than 1 MHz, for the first time, to our knowledge, in intrinsically stretchable electronics. Moreover, we demonstrate a high-throughput braille recognition system that surpasses human skin sensing ability, enabled by an active-matrix tactile sensor array with a record-high density of 2,500 units per cm2, and a light-emitting diode display with a high refreshing speed of 60 Hz and excellent mechanical robustness. The above advancements in device performance have substantially enhanced the abilities of skin-like electronics.

An efficient algorithm for estimating gate-level power consumption in large-scale integrated circuits

Estimating power dissipation in Very Large Scale Integrated (VLSI) circuits, particularly large-scale sequential circuits, is a significant challenge in Electronic Design Automation (EDA). Benchmarked against PrimeTime PX, the proposed algorithm proficiently analyzes large-scale combinational and sequential circuits. This research begins with a power analysis algorithm for combinational circuits, focusing on signal probability (SP) and transition count (TC). It then extends to sequential circuits, introducing methodologies for loopback issues and a validity-checking mechanism for spatial dependency topology. Developed on the OpenTimer open-source framework using the SMIC 40-nm process library, the algorithm was validated on academic and industrial datasets. Experimental evaluations show that our algorithm outperforms in terms of speed and accuracy. For power analysis with vector annotations, it achieves an average error within 0.16% in power testing of large-scale timing circuits. It also performs gate-level vectorless power analysis on complex topology and large-scale integrated circuits, demonstrating computational robustness.

Low-temperature process design for inversion mode n-channel thin-film-transistor on polycrystalline Ge formed by solid-phase crystallization

We fabricated an inversion mode n-channel thin-film-transistor (TFT) on polycrystalline (poly-) Ge at low temperatures for monolithic three-dimensional large-scale IC (3D-LSI) and flexible electronics applications. Based on our previously reported solid-phase crystallization (SPC) method, we designed an n-channel TFT fabrication process with phosphorous ion implantation to provide the source/drain (S/D). We succeeded in fabricating an n-channel TFT with typical electrical characteristics on poly-Ge and confirmed its operation mode to be inversion mode. However, the fabrication process included a high temperature (500 °C) step for S/D activation. To reduce the process temperature, we used a metal-induced dopant activation method and successfully reduced the activation temperature to 360 °C. This combination is expected to pave the way for high-performance 3D-LSI and flexible electronic devices based on SPC-Ge.

IMPACT OF SUPPLY VOLTAGE ON SRAM CELL POWER DISSIPATION UNDER DIFFERENT TOPOLOGIES

The high storage density and quick access times of Static Random Access Memory (SRAM) make it a critical component of many Very Large Scale Integration circuits. However, device scaling in today's technology leads to an increase in dynamic power and a decrease in noise margin, posing significant challenges to memory circuit design for the next generation of devices. In addition, sub-threshold leakage is also a concern. In recent years, the increasing demand for notebooks, laptops, IC memory cards, and mobile communication devices has driven the development of low-power, low-voltage memory circuits. Static Random Access Memoryis widely used as on-chip and off-chip memory for portable applications because they are easy to use and have minimal standby leakage. Since 60% to 70% of the chip memory is used, SRAM optimization is the focus of research. The SRAM cell's architecture and performance have been studied using various technologies to minimize power dissipation while maintaining stability. Based on the power dissipation, including static and dynamic power dissipation, and Static Noise Margin (SNM), the SRAM cell performance is compared with different topologies. The SNM fluctuation is considered along with the variation of supply voltage.

Estimating R, L and C in Arithmetic Circuits using ML

In Very Large Scale Integration (VLSI) circuits, the estimation techniques for resistors (R), inductors (L), and capacitors (C) heavily rely on segmented circuit analysis, which involves usage of complex mathematical simplification models. These methods have been conventionally applied to estimate the behavior of circuits, but when faced with systems featuring unique circuit architectures, they often encounter inaccuracies and limitations. The significance of adders as fundamental building blocks in intricate circuit design cannot be overstated. In such complex circuits, various parameters, including parasitic resistances, inductances, and capacitances, engage an indispensable effort in the analysis of delays and performance. However, the conventional estimation methods fail to address the complexities of these systems and the impacts of parasitics accurately. To overcome these challenges, this paper proposes a novel approach that harnesses the potential of machine learning algorithms. By integrating machine learning into the estimation process, the research aims to achieve specific and precise analysis methods that can cater to the needs of modern VLSI circuits. The proposed methodology involves collecting a comprehensive dataset using different adder circuits. From each individual adder circuit layout, the relevant information on resistors, capacitors, and inductors is carefully extracted and compiled. This dataset serves as the foundation for training the machine learning models. Three standard machine learning models are employed in this study: adaboost, Tree, and k-Nearest Neighbors (kNN). Their task is to predict the values of resistors, inductors, and capacitors based on the input data from the adder circuits. Among these models, adaboost proves to be the most effective, exhibiting superior performance by achieving a reduced root mean square error of about 0.008. When compared to the Tree and kNN models, adaboost stands out as the optimal choice for accurately estimating the R values in VLSI circuits.

High-Q adiabatic micro-resonators on a wafer-scale ion-sliced 4H-silicon carbide-on-insulator platform.

A 4H-silicon carbide-on-insulator (4H-SiCOI) has emerged as a prominent material contender for integrated photonics owing to its outstanding material properties such as CMOS compatibility, high refractive index, and high second- and third-order nonlinearities. Although various micro-resonators have been realized on the 4H-SiCOI platform, enabling numerous applications including frequency conversion and electro-optical modulators, they may suffer from a challenge associated with spatial mode interactions, primarily due to the widespread use of multimode waveguides. We study the suppression of spatial mode interaction with Euler bends, and demonstrate micro-resonators with improved Q values above 1 × 105 on ion-sliced 4H-SiCOI platform with a SiC thickness nonuniformity less than 1%. The spatial-mode-interaction-free micro-resonators reported on the CMOS-compatible wafer-scale 4H-SiCOI platform would constitute an important ingredient for the envisaged large-scale integrated nonlinear photonic circuits.

Very Large-Scale Integration Circuit and Its Current Status Analysis

The development of Very Large Scale Integration (VLSI) has become very relevant to our lives, and although many of the technologies have matured, scientists are still actively exploring and innovating them. This article is a basic introduction to the composition and advanced technology of large-scale integrated circuits, focusing on transistors and the basic components it consists of, as well as the design of integrated circuits, manufacturing and measurement technology. Very Large Scale Integration Circuit, the transistor is the most basic component of the original, to the low-power CMOS tube is the most widely used, they form a logic gate and storage elements, to achieve a variety of basic functions of the circuit, while the circuit also exists to provide signal distribution and interconnection of the clock network, the optimization of the design of the contemporary research is also a hot spot. In recent years, the progress of the chip can not be separated from the development of new technologies, SOC technology, low-power technology and detection technology plays an important role in the promotion.

Novel methods for locating and matching IC cells based on standard cell libraries

In the domain of hardware assurance, reverse engineering (RE) is essential for ensuring the security and reliability of integrated circuits (ICs). A potential approach in the crucial step of netlist extraction involves matching patterns in IC images to standard cell libraries. However, the morphological variations in images of cells and intra-cell similarities present significant challenges to effective matching. This paper introduces a new matching dataset of cells in Scanning Electron Microscopy (SEM) images and standard cells, including 579 SEM cells, two standard cell libraries, and 508 types of standard cells. Furthermore, we propose a novel matching method reliant on standard cell libraries. This method generates templates using the feature information of standard cells and conducts matching by comparing the similarity between the feature vector sets of an SEM cell and the templates, achieving a 100% accuracy rate on the matching dataset. Given that the matching method relies on accurate cell localization, we propose two methods of merging bounding boxes. These methods can convert the object detector's detection results on patches into localization results on the entire image, achieving 99.48% accuracy and 99.31% recall on the image of the matching dataset. Finally, We consolidate these methods into a comprehensive workflow for automating the extraction of cell information in large-scale IC images.

Tunneling Current Variations in Small-Sized Devices Based on a Compact Threshold Voltage Model

Accurate modeling of threshold voltage is necessary in the integrated circuit design of strained silicon devices. Thoroughly researching the factors that affect threshold voltage and establishing a more precise threshold voltage model, can provide essential theoretical support for integrated circuit design. By solving a Poisson equation, in this paper, we demonstrate a comprehensive physical model for the threshold voltage of strained Si NMOSFETs using the gradual channel approximation theory and a quasi-two-dimensional analysis. The model investigates the physical effects such as short-channel, narrow-channel, non-uniform doping, and drain-induced barrier lowering effects on the threshold voltage. After substituting the extracted parameters into the model, a comparison was made with experimental results to validate the accuracy and correctness of the established model. Additionally, variations in the tunneling current of small-sized devices were studied. The two models provide essential references for the analysis and design of strained Si large-scale integrated circuits.

Efficient Sigma-Delta Sensor Array Beamforming.

Nowadays, sensors with built-in sigma-delta modulators (ΣΔMs) are widely used in consumer, industrial, automotive, and medical applications, as they have become a cost-effective and convenient way to deliver data to digital processors. This is the case for micro-electro-mechanical system (MEMS), digital microphones that convert analog audio to a pulse-density modulated (PDM) bitstream. However, as the ΣΔMs output a PDM signal, sensors require either built-in or external high-order decimation filters to demodulate the PDM signal to a baseband multi-bit pulse-code modulated (PCM) signal. Because of this extra circuit requirement, the implementation of sensor array algorithms, such as beamforming in embedded systems (where the processing resources are critical) or in very large-scale integration (VLSI) circuits (where the power and area are crucial) becomes especially expensive as a large number of parallel decimation filters are required. This article proposes a novel architecture for beamforming algorithm implementation that fuses delay and decimation operations based on maximally flat (MAXFLAT) filters to make array processing more affordable. As proof of concept, we present an implementation example of a delay-and-sum (DAS) beamformer at given spatial and frequency requirements using this novel approach. Under these specifications, the proposed architecture requires 52% lower storage resources and 19% lower computational resources than the most efficient state-of-the-art architecture.

Unsupervised graph-based image clustering for pretext distribution learning in IC assurance

Delayered integrated circuit (IC) image analysis is one of the most reliable approaches for the hardware assurance of ICs. Deep learning (DL) techniques have been proposed as an effective means to automate IC image analysis due to their high accuracy and efficiency, allowing for automated learning from labeled training data. These data-driven approaches typically require a large amount of comprehensive training samples that are representative of the testing dataset. Curating such suitable datasets for deep learning training is a challenging and time-consuming task, especially when working with large-scale IC image datasets. Automatically analyzing the distribution of the IC images would be an efficient method to curate ideal datasets for deep learning. In this paper, we propose an unsupervised graph-based image clustering framework for pretext distribution learning of delayered IC images. Our proposed framework consists of a pre-trained convolutional neural network (CNN) in the feature extraction stage, a graph-based feature clustering stage, and an image retrieval stage. In our experiments, we achieved a best normalized mutual information score of 0.6407 for the clustering of a benchmark dataset containing 1911 delayered IC images. Our framework has excellent ability to retrieve visually similar images from the benchmark dataset when queried with unseen image samples.

Low power flexible monolayer MoS2 integrated circuits

Monolayer molybdenum disulfide (ML-MoS2) is an emergent two-dimensional (2D) semiconductor holding potential for flexible integrated circuits (ICs). The most important demands for the application of such ML-MoS2 ICs are low power consumption and high performance. However, these are currently challenging to satisfy due to limitations in the material quality and device fabrication technology. In this work, we develop an ultra-thin high-κ dielectric/metal gate fabrication technique for the realization of thin film transistors based on high-quality wafer scale ML-MoS2 on both rigid and flexible substrates. The rigid devices can be operated in the deep-subthreshold regime with low power consumption and show negligible hysteresis, sharp subthreshold slope, high current density, and ultra-low leakage currents. Moreover, we realize fully functional large-scale flexible ICs operating at voltages below 1 V. Our process could represent a key step towards using energy-efficient flexible ML-MoS2 ICs in portable, wearable, and implantable electronics.

Stability and Power Analysis of Schmitt Trigger Based Low Power SRAM Bit-Cell Using CMOS and CNTFET Technology at 22nm Technology Node

SRAM (Static Random Access Memory) is an essential component of memory devices such as laptops, phones, etc., which act as a semiconductor memory. The “Carbon Nanotube Field Effect Transistor (CNTFET)” is silicon associated high-stability, low-power device with excellent performance. CNTFET has been verified to be very advantageous for Very large-scale integration circuit designs in the nanoscale range because of its remarkable properties of metal oxide semiconductor field effect transistor (MOSFET). The material was brought to light because of its genuinely incredible electrochemical performance. Carbon nanotubes have unique properties such as high charge carrier mobility, high voltage, small footprint, exceptionally short and high control over pulse duration, and large current densities. In traditional MOSFET, bulk silicon is used, which has high leakage current and high field-effect; thus, CNTFET has been used as an alternative in recent years. When compared to the 10T CNTFET SRAM Bit cell is designed using HSPICE Tool in 22nm technology. Long-term stability and significant process variable changes are significant challenges with nanoscale SRAM cells.

A Deep Learning Framework for Solving Stress-based Partial Differential Equations in Electromigration Analysis

The electromigration-induced reliability issues (EM) in very large scale integration (VLSI) circuits have attracted continuous attention due to technology scaling. Traditional EM methods lead to inaccurate results incompatible with the advanced technology nodes. In this article, we propose a learning-based model by enforcing physical constraints of EM kinetics to solve the EM reliability problem. The method aims at solving stress-based partial differential equations (PDEs) to obtain the hydrostatic stress evolution on interconnect trees during the void nucleation phase, considering varying atom diffusivity on each segment, which is one of the EM random characteristics. The approach proposes a crafted neural network-based framework customized for the EM phenomenon and provides mesh-free solutions benefiting from the employment of automatic differentiation (AD). Experimental results obtained by the proposed model are compared with solutions obtained by competing methods, showing satisfactory accuracy and computational savings.

An Enhanced Deep Reinforcement Learning-Based Global Router for VLSI Design

Global routing is a crucial step in the design of Very Large-Scale Integration (VLSI) circuits. However, most of the existing methods are heuristic algorithms, which cannot conjointly optimize the subproblems of global routing, resulting in congestion and overflow. In response to this challenge, an enhanced Deep Reinforcement Learning- (DRL-) based global router has been proposed, which comprises the following effective strategies. First, to avoid the overestimation problem generated by Q -learning, the proposed global router adopts the Double Deep Q -Network (DDQN) model. The DDQN-based global router has better performance in wire length optimization and convergence. Second, to avoid the agent from learning redundant information, an action elimination method is added to the action selection part, which significantly enhances the convergence performance of the training process. Third, to avoid the unfair allocation problem of routing resources in serial training, concurrent training is proposed to enhance the routability. Fourth, to reduce wire length and disperse routing resources, a new reward function is proposed to guide the agent to learn better routing solutions regarding wire length and congestion standard deviation. Experimental results demonstrate that the proposed algorithm outperforms others in several important performance metrics, including wire length, convergence performance, routability, and congestion standard deviation. In conclusion, the proposed enhanced DRL-based global router is a promising approach for solving the global routing problem in VLSI design, which can achieve superior performance compared to the heuristic method and DRL-based global router.

Giant enhancement of the Goos–Hanchen shift based on quasi-bound states in the continuum in terahertz band through silicon based metasurface

By breaking the symmetry of the structure, we obtain bound states in the continuum (BIC) in terahertz (THz) using metasurfaces which were prepared with Si and/or Si-compatible materials. With the help of the quasi-BIC with an ultra-high Q factor, the enhanced Goos–Hanchen (GH) shift can reach 5812 times of wavelength. At the same time, the high reflectance is maintained, which makes up for the defect of low reflectance when the GH shift is enhanced by the Brewster angle effect and transmission-type resonances and is convenient for experimental measurement. In addition, the metasurface can be used as an environmental refractive index sensor, and its maximum sensitivity can reach 1.27 × 107mm/RIU, which promotes the development of THz high-resolution sensors. The results could boost the development of silicon-photonics to provide low-cost, highly efficient integrated devices benefited from the same fabrication process as that of large-scale integrated circuit production.

Terminal Atom-Controlled Etching of 2D-TMDs.

The controlled etching of 2D transition metal dichalcogenides (2D-TMDs) is critical to understanding the growth mechanisms of 2D materials and patterning 2D materials but remains a major comprehensive challenge. Here, a rational strategy to control the terminal atoms of 2D-TMDs etched holes is reported. Using laser irradiation combined with an improved anisotropic thermal etching process under a determined atmosphere, terminal atom-controlled etched hole arrays are created on 2D-TMDs. By adjusting the gas atmosphere during the thermal etching stage, triangular etched hole arrays terminated by the tungstenzigzag(W-ZZ) edge (in an Ar/H2 atmosphere), hexagonal etched hole arrays terminated alternately by the W-ZZ edge and sulfur(selenium)zigzag(S-ZZ orSe-ZZ) edge (in a pure Ar atmosphere), and triangular etched hole arrays terminated by the S-ZZ (Se-ZZ) edge (in an Ar/sulfur [selenium] vapor atmosphere) can be obtained. Density functional theory reveals the forming energy of different edges and the different activities of metal atoms and chalcogenide atoms under different atmospheres, which determine the terminal atoms of the holes. This work may enhance the understanding of the etching and growth of 2D-TMDs. The 2D-TMDs hole arrays constructed by this work may have important applications in catalysis, nonlinear optics, spintronics, and large-scale integrated circuits.