Large Memory Window Research Articles

Performance Improvement of Hf0.5Zr0.5O2-Based Ferroelectric-Field-Effect Transistors With ZrO2 Seed Layers

Hf0.5Zr0.5O2(HZO)-based ferroelectric-field-effect transistor (FeFET) with a ZrO2 seed layer was demonstrated. It was found that the ZrO2 seed layer could effectively improve the ferroelectric properties of the (hafnium zirconium oxide) HZO thin film. The remanent polarization and the coercive voltage of the metal–ferroelectric–insulator–semiconductor (MFIS) structure with the ZrO2 seed layer were larger than those without the seed layer. Moreover, the FeFET with the ZrO2 seed layer showed wider counterclockwise hysteresis loops in the transfer characteristics than that without the seed layer, achieving a large memory window of about 2.8 V. These results validate the advantages of the ZrO2 seed layer in promotion of FeFET performance and thus warrant further study.

Design of high performance MoS2-based non-volatile memory via ion beam defect engineering

Nonvolatile charge trap memory is an important part of the continuous development of information technology. As a 2-dimensional (2D) material with fantastic physical characteristics, molybdenum disulfide (MoS2) has been receiving extensive attention for its potential applications in electronic devices. However, while various attempts have been made to devise its charge-trap gate stack, it’s still impossible to avoid a certain performance degradation. Here, a MoS2-based nonvolatile charge trapping memory device with a charge-trap gate stack formed by implanting N ions into SiO2 is reported. The fabricated N-implanted memory devices with the energy of 6.5 keV and the dose of 1 × 1015 ions cm−2 exhibit a high on/off current ratio up to 107, a large memory window of 9.1 V, and a high program/erase speed of 10/100 µs. Moreover, the memory device shows an excellent cycling endurance of more than 104 cycles. By combining the MoS2 channel with the N-implanted charge-trap gate stack, this research opens up a fascinating field of nonvolatile charge trap memory devices.

High‐Performance Organic Field‐Effect Transistor with Matching Energy‐Band Alignment between Organic Semiconductor and the Charge‐Trapping Dielectric

AbstractHigh‐performance bottom‐gate nonvolatile organic field‐effect transistor (OFET) devices based on a special matching energy‐band alignment between the organic semiconductor pentacene and the charge‐trapping dielectric ZnTe are reported. The lower potential difference between the conduction band minimum of ZnTe and the lowest unoccupied molecular orbital of pentacene with a weak electron conductivity endows the OFET a memory window of 10 V at an applied sweeping gate‐voltage of ±15 V, a high ION/IOFF ratio of more than 106, and good retention with a high ION/IOFF ratio of 6 × 105 after 104 s. The large memory window of the OFET is attributed to the unique energy‐band alignment of the memory device and the high density of traps in Te‐deficient ZnTe film, and the prominent retention is attributed to the deeply trapped electrons in the potential well formed by Al2O3 tunneling and blocking layers.

Improvement in Resistance Switching of SiC-Based Nonvolatile Memory by Solution-Deposited HfOx Thin Film.

In this study, we implemented a resistance change memory (ReRAM) device using a SiC layer with excellent physical properties. We fabricated devices composed of Ti/SiC/Pt and Ti/HfOx/SiC/Pt structures and investigated their memory characteristics. The Ti/SiC/Pt ReRAM devices exhibited stable bipolar resistive switching characteristics but had a relatively small memory window, whereas the Ti/HfOx/SiC/Pt ReRAM devices had a large memory window and low operating voltage. In addition, the Ti/HfOx/SiC/Pt ReRAM devices exhibited stable endurance characteristics over 500 cycles and excellent retention characteristics at room temperature and high temperatures for 1×10⁴ s. Further, the Ti/HfOx/SiC/Pt ReRAM devices exhibited multi-level conduction states by modulating the reset stop voltage, and each resistance level had excellent endurance characteristics. The average transmittance of the HfOx/SiC bilayer in visible light was 87%. Such a high value indicates that the HfOx/SiC bilayer fabricated by the stacking method is expected to be a suitable material for highly reliable nonvolatile memory and transparent electronic devices, even in harsh environments.

A unipolar nonvolatile resistive switching behavior in a layered transition metal oxide.

Two-dimensional layered materials have been considered as promising candidates for resistive random access memory, one of the most promising next-generation nonvolatile memories. However, due to the types of defects, most of the devices still suffer from poor environmental stability, defects inducing complexity, and uncontrollability. Here, we fabricate memory cells based on synthesized high-quality two-dimensional layered transition-metal oxide (α-MoO3) nanosheets which can be thinned to 8.68 nm (∼6 layers) and find a unipolar nonvolatile resistive switching behavior. Driven by the migration of intrinsic oxygen vacancies, the devices show a large memory window (∼105), good memory voltage stability, long-term endurance (for durations of over 3 days and 50 manual DC switching cycles) and multi-bit memory states. Furthermore, we find the devices with an excellent temperature tolerance of lower SET/RESET voltages and a larger memory window (>104 at 380 K) at higher temperatures, suggesting their potential in practical applications. Finally, all 2D memory devices are demonstrated using graphene/α-MoO3/graphene heterostructures.

Impacts of HfO2/ZnO Stack-Structured Charge-Trap Layers Controlled by Atomic Layer Deposition on Nonvolatile Memory Characteristics of In-Ga-Zn-O Channel Charge-Trap Memory Thin-Film Transistors

We fabricated the charge-trap memory thin film transistors (CTM-TFTs) using InGaZnO (IGZO) active channel and HfO2/ZnO stack-structured charge-trap layer (CTL). To investigate the effects of the number and thickness of HfO2 layers inserted between the ZnO within the stack structured CTLs on the device characteristics, 2-nm-thick HfO2 thin films were inlaid once, twice, and four times, and 4-nm-thick HfO2 layers were introduced twice between the ZnO layers. The CTM-TFTs using the stack structured CTLs with 4-nm-thick HfO2 layers showed good memory characteristics, including large memory window (MW) of 25 V and rapid program/erase (P/E) speed of 500 $\mu \text{s}$ because of high total trap density of HfO2 with a sufficient thickness to provide charge-trap centers. On the contrary, relatively narrow MW of 16 V and slower P/E speed of 100 ms were obtained for memory device using the stacked CTL with four HfO2 layers of 2 nm. The HfO2 layer with a thickness as thin as 2 nm was supposed to act as just dielectric films deactivating the trapping or migration of electron charges due to too thin film thickness. The gate-stack structures confirmed from STEM images suggested that the modulations in memory device characteristics with different CTL structures resulted from the variations in designs of stack structured CTLs when the interface qualities within the gate-stacks were well prepared. Moreover, the detailed fabrication conditions were found to be important control parameters to reproducibly obtain reliable memory device characteristics.

Multilevel resistive and magnetization switching in Cu/CoFe2O4/Pt device: Coexistence of ionic and metallic conducting filaments

Non-volatile, multilevel bipolar Resistive Switching (RS) along with multilevel magnetization switching, in a cobalt ferrite (CFO) thin film using a simple Cu/CFO/Pt sandwich structure, has been demonstrated. Besides the low resistance state (LRS) and the high resistance state (HRS), the device exhibits two intermediate resistance states (IRSs), which are stable with time and reproducible in RS cycles. The endurance characteristics of the present RS device (>500 switching cycles) show no noticeable degradation and the ultimate resistance ratio always remains >104, which ensures reproducibility, reversibility, and controllability of the RS features of the present device. The HRS of the device shows a semiconducting conduction mechanism, whereas the LRS and both the IRSs were found to be Ohmic in nature. Simultaneous magnetization and resistive switching confirmed the multifunctional behavior of the device and suggested the presence of a valence change mechanism of resistive switching. The magnetization vs. magnetic field studies and temperature dependent resistance studies revealed that the electrochemical metallization also plays an important role during the switching process, which enhances the resistance ratio by providing an additional metallic filament of Cu atoms along with the ionic conducting filament of oxygen vacancies. The voltage controlled multilevel magnetization and resistive switching with a large memory window (resistance ratio >104) make the present device a potential candidate for paving the path for future multifunctional and multilevel memory devices with the capability of high density data storage.

Organic transistor nonvolatile memory with an integrated molecular floating-gate/tunneling layer

Floating-gate based organic field-effect transistor (FG-OFET) nonvolatile memories (NVMs) are demonstrated based on an integrated molecular floating-gate/tunneling layer, in which small molecular fullerene (C60) acting as the floating-gate and long-chain alkane molecule tetratetracontane acting as the tunneling layer are synchronously prepared by vacuum thermal evaporation. The effects of the thickness and the component of the integrated floating-gate/tunneling layer on the performances of memory are investigated. As a result, a high performance FG-OFET NVM is achieved, with a large memory window of 8.0 V on average, stable retention capability over 10 years, and reliable switching endurance over 100 cycles at the programming/erasing voltages of ±40 V, at an optimized condition.

Performance enhancement of nonvolatile memory by using a trapping layer of graphene oxide quantum dots

In this study, we studied and fabricated two nonvolatile memory devices based on Pd/SiO2/ZnO/SiO2/p-Si and Pd/SiO2/ZnO/GOQDs/ZnO/SiO2/p-Si structures. From the device measurements, it can be seen that the ZnO/GOQDs/ZnO samples exhibit a very large memory window (up to 1.86 V) when the gate sweeping voltage is ±4 V, in contrast to a memory window (up to 1.05 V) for a single layer of ZnO sample under a gate sweeping voltage of ±8 V. The surface trap charge density of ZnO/GOQDs/ZnO samples is about 1.57 × 1011cm−2, and the charge loss is only 8% after a retention time of 104 s. These remarkable memory properties are mainly due to GOQD’s deep quantum potential traps and discrete distributions. The high potential barrier suppresses the reverse tunneling, thereby preventing leakage current. We conclude that the integration of GOQD in memory devices is compatible with semiconductor manufacturing processes, so the proposed device architecture is promising to achieve large memory window characteristics, low power consumption, and long data retention time.

A Tunneling Dielectric Layer Free Floating Gate Nonvolatile Memory Employing Type-I Core-Shell Quantum Dots as Discrete Charge-Trapping/Tunneling Centers.

A nonvolatile memory with a floating gate structure is fabricated using ZnSe@ZnS core-shell quantum dots as discrete charge-trapping/tunneling centers. Systematical investigation reveals that the spontaneous recovery of the trapped charges in the ZnSe core can be effectively avoided by the type-I energy band structure of the quantum dots. The surface oleic acid ligand surrounding the quantum dots can also play a role of energy barrier to prevent unintentional charge recovery. The device based on the quantum dots demonstrates a large memory window, stable retention, and good endurance. What is more, integrating charge-trapping and tunneling components into one quantum dot, which is solution synthesizable and processible, can largely simplify the processing of the floating gate nonvolatile memory. This research reveals the promising application potential of type-I core-shell nanoparticles as the discrete charge-trapping/tunneling centers in nonvolatile memory in terms of performance, cost, and flexibility.

Demonstration of α-InGaZnO TFT Nonvolatile Memory Using TiAlO Charge Trapping Layer

Amorphous indium gallium zinc oxide (α-InGaZnO) thin-film transistors using as nonvolatile memories (TFT-NVMs) with an Al2O3/TiAlO/Al2O3 charge trapping engineered structure have been demonstrated experimentally at low thermal budget of 300 °C. The high- k composite TiAlO layer with a high trap state density and a high dielectric constant was prepared by sputtering at room temperature as a charge trapping material. According to the high-resolution transmission electron microscopy analyses, the Al2O3/TiAlO/Al2O3 gate stack exhibited sharp interfaces and a uniform distribution of Ti and Al elements in the TiAlO film. The programming and retention characteristics of the fabricated α-InGaZnO TFT-NVMs were investigated in detail. The TFT-NVMs exhibited excellent programming characteristics with a large memory window of around 5.74 V under a 16 V programming voltage. It can also maintain a memory margin of about 5 V after 10 years, indicating only ∼15% charge loss. This paper suggests that α-InGaZnO TFT-NVMs using the high- k TiAlO composite material as the charge trapping material are promising for future nonvolatile memories applications in display technology, flexible and wearable electronics.

Outstanding memory characteristics with atomic layer deposited Ta2O5/Al2O3/TiO2/Al2O3/Ta2O5 nanocomposite structures as the charge trapping layer

A charge trapping memory device using Ta2O5/Al2O3/TiO2/Al2O3/Ta2O5 (TATiAT) nanocomposite high-k dielectrics as charge trapping layer (CTL) and amorphous Al2O3 as the tunneling and blocking layers has been investigated, in which all the high-k dielectric films were fabricated by atomic layer deposition (ALD) technique. A large memory window of 10.0 V with higher charge trap density of 1.10 × 1013 cm−2 at gate voltage of ±10 V has been achieved. The better storage characteristic is attributed to the inter-diffusion between nanocomposite high-k oxides and the formation of more oxygen vacancies in CTL. The device shows the fast P/E speed and excellent endurance characteristics. A 70% initial memory window can be maintained after 10 years of retention by using the extrapolation method. The large conduction band offsets of 1.02 eV between TATiAT and Al2O3 is beneficial to retention characteristic due to the deep trap level.

Exploring the role of nitrogen incorporation in ZrO2 resistive switching film for enhancing the device performance

The role of nitrogen doping on the resistive switching (RS) performance in nitrogen doped ZrO2 memristive device is investigated. The Pt/N:ZrO2/TiN resistive random access memory (RRAM) shows smaller switching voltage, larger memory window as well as improved uniformity. Moreover, the multilevel storage capability can be successfully obtained by varying the compliance current in the SET process for the memory cell. It is considered that the connection and rupture of conducting oxygen vacancy filaments (CF) can be localized and the oxygen ions (O2−) migration randomness is depressed due to nitrogen doping in ZrO2 film. Combining with the first-principle method, we theoretically calculate the formation energy (Evf), migration energy (Em) and density of states for oxygen vacancy (VO). Both Evf and Em values show noticeable decrease in N doped 2 × 2 × 2 ZrO2 supercell, which are related to the lower forming voltage and operating voltage. The density of states indicates that the oxygen vacancy midgap defect states can be eliminated as a result of N dopant, which neutralizes the excess defects in ZrO2 switching layer and may reduce the densities of the potential filaments. Herein the uniformity can be improved. All the theoretical results show reasonable agreement with the improved experimental RS performance for Pt/N:ZrO2/TiN device.

Nonvolatile Memory Based on Molecular Ferroelectric/Graphene Field Effect Transistor

Ferroelectric thin films are extensively attractive as next-generation nonvolatile memories. Recently, molecular ferroelectrics (MFe), as an emerging new class, have been a new research focus because of their desirable characteristics such as good solution processability, tunable chemical properties, and bio-friendly compositions. However, traditional uniaxial MFe only possess one polar axis which greatly limits their application, as it requires restricted orientational control in single crystal. To achieve macroscopic ferroelectricity and thus fully realize technological advantages of MFe, development of multiaxes is imperative to maximize effective polarization in specific crystallographic orientations. Herein, we present an early exploration on polycrystalline multiaxial MFe thin films of [Hdabco][ReO4] with a two-dimensional graphene hybrid nonvolatile memory device. The polarization switching of MFe is experimentally realized by the nonvolatile modulation of two current states in graphene. Such a hybrid device can exhibit large memory window ∼35 V implying its great potential in memory applications. Hence, by taking the advantages of multiple polarization axes of MFe, the low cost and large area MFe/graphene hybrid memory manifests new possibilities for the integration of these materials as flexible next generation memory devices.

4,5-Diazafluorene-Based Donor-Acceptor Small Molecules as Charge Trapping Elements for Tunable Nonvolatile Organic Transistor Memory.

Three diazafluorene derivatives triphenylamine (TPA)(PDAF)n (n = 1, 2, 3) serving as small molecular elements are designed and synthesized via concentrated sulfuric acid mediated Friedel–Crafts reaction. With highly nonplanar topological configuration, TPA(PDAF)3 shows weaker intermolecular interaction in the solid states and thus exhibits single nanomolecular behavior, which is crucial for charge stored and retained in an organic field‐effect transistor (OFET) memory device. Furthermore, diazafluorene derivatives possess a completely separate highest occupied molecular orbital/lowest unoccupied molecular orbital, which offers ideal hole and electron trapping sites. As charge storage elements, triphenylamine groups provide the hole trapping sites, while diazafluorene units provide the electron trapping sites and act as a hole blocking group to restrain the leakage of stored holes trapped in triphenylamine. The pentacene‐based OFET memory device with solution‐processing TPA(PDAF)3 shows a good hole‐trapping ability, high hole trapping density (4.55 × 1012 cm−2), fast trapping speed (<20 ms), a large memory window (89 V), and a tunable ambipolar memory behavior. The optimized device shows a large ON/OFF current ratio (2.85 × 107), good charge retention (>104 s), and reliable endurance properties. This study suggests that diazafluorene based donor–acceptor small molecular elements have great promise for high‐performance OFET memory.

Wafer-scale very large memory windows in graphene monolayer/HfZrO ferroelectric capacitors

We have fabricated and electrically characterized at the wafer scale tens of metal-ferroelectric (HfZrO)-semiconductor capacitors and metal-graphene monolayer-ferroelectric (HfZrO)-semiconductor capacitors with the same top electrode dimensions. We have found that the memory windows of the capacitors containing graphene are 3–4 times larger than the ferroelectric capacitors without graphene, and increase even more after annealing. This physical effect can be attributed to the additional electric field exerted by the graphene monolayer on the HfZrO ferroelectric semiconductor capacitor, and to the negative thermal extension coefficient of graphene, respectively.

High capacity organic memory structures based on PVP as the insulating layer

The electrical behaviour of organic memory structures based on gold nanoparticles (AuNPs) and poly 4-vinylphenol as the gate dielectric are reported in this work. Metal–insulator–semiconductor (MIS) and thin film transistor structures were used to fabricate the control and memory devices. The drain and source electrodes were fabricated by evaporating 50 nm gold, and the gate electrode was made from 50 nm-evaporated aluminium on a clean glass substrate. Thin films of AuNps embedded within the insulating layer were used as the floating gate. All memory devices exhibited clear hysteresis in their electrical characteristics [capacitance–voltage (C–V) for MIS structures as well as output and transfer characteristics for transistors]. Both structures were shown to produce reliable and large memory windows by virtue of high capacity. The hysteresis in the output and transfer characteristics and shifts in the threshold voltage of the transfer characteristics as well as flat-band voltage shift in the MIS structures were attributed to the charging and discharging of the AuNPs floating gate. Memory window of 38 V was achieved by scanning the applied voltage of the MIS structure between 40 and − 40 V. Similarly, a memory window of 27 V was achieved for the TFT-based memory structure. Under an appropriate gate bias of 1 s pulses, the floating gate is charged and discharged, resulting in significant threshold voltage shifts. Pulses of as low as 5 V resulted in a clear write and erase states.

An electronic synaptic device based on HfO2TiOx bilayer structure memristor with self-compliance and deep-RESET characteristics

We reported on a Ti/HfO2/TiOx/Pt memristor with self-compliance, deep-RESET characteristics and excellent switching performance, including ultrafast program/erase speed (10 ns), a large memory window (103) and good pulse endurance (107 cycles). The self-compliance and deep-RESET characteristics are beneficial for protecting the device from permanent breakdown in both SET and RESET processes especially under the pulse operation mode. In addition to bistable state switching, we also achieved multiple or even continuous conductance state switching under a DC sweep and a pulse-train operation mode in the Ti/HfO2/TiOx/Pt memristor, which can be seen as a substitution of a biological synapse. The capability of continuous modulation conductance (synaptic weight) in the Ti/HfO2/TiOx/Pt memristor was investigated and the potentiation and depression characteristics of the synaptic weight could be precisely tuned by the number or amplitude of the input pulse-train. Moreover, clear experimental evidence of short-term plasticity (STP) and long-term plasticity (LTP) in a single memristor was also demonstrated. Increasing the pulse amplitude or width, or decreasing the interval of two adjacent pulses of the input pulse-train resulted in the memristor behavior transitioning from STP to LTP. The realization of those important synaptic functions in the Ti/HfO2/TiOx/Pt memristor may be suitable for applications in artificial neural systems.

Effect of microwave irradiation power on resistive switching performance in solution-processed aluminum oxide resistive memory

In this study, we fabricated ReRAM devices with the structure Ti/AlOx/Pt by applying solution-processed AlOx film as the switching layer. This enabled us to analyze the effect of the MWI power on the resistive switching performance of ReRAM. The AlOx resistive switching layer deposited by the solution-process was subjected to PDA treatment with microwave power ranging from 600 W to 3000 W, and the resistive switching performance was compared with as-dep and CTA-processed ReRAMs. All AlOx-based ReRAM devices exhibited bipolar resistive switching characteristics, and MWI-treated devices had larger memory windows than as-dep and CTA-treated devices. These solution-processed AlOx ReRAMs were found to exhibit Ohmic conduction in the low-voltage range of both the LRS and HRS. The high-voltage range of HRS shows the Poole-Frenkel conduction mechanism. In addition, compared with the as-dep device, the PDA-treated devices exhibited stable endurance characteristics and uniform resistance distribution in 1000 cycles of the switching operation, and showed reliable retention characteristics for 10,000 s at both room temperature and high temperature. XPS measurements were performed to analyze the relationship between the resistive switching performance and chemical nature of the AlOx switching layer by varying the microwave power and heat treatment method.

Visible-light enhanced charge storage characteristics of amorphous Ni-doped HfO2 films

Photo-induced changes of capacitance–voltage curves for amorphous Ni-doped HfO2 films are probed under different visible light illumination conditions. The illumination-induced minority carriers injection effect enhances the negative shift of flat band voltage, and results in a significant enlargement of memory window. This enlargement exhibits negligible dependence on light wavelength but strong dependence on light intensity in the visible light region. A large memory window width of 6.12 V is obtained under illumination using 650 nm red light with an intensity of 5 mW cm−2. Acceptable endurance and retention properties show potential applications on new-type photosensitive nano-floating-gate nonvolatile memory devices.