Large Leakage Current Research Articles

AlGaN/GaN Heterostructure Schottky Barrier Diodes with Graded Barrier Layer

The AlGaN/GaN Schottky barrier diodes (SBDs) working as high-power mixer and multiplier show great potential in millimeter wave (MMW) field owing to their high breakdown voltage. Nevertheless, its further application is severely limited by large reverse leakage current (Jr) since the two-dimensional electron gas (2DEG) channel is hard to be pinched off at low voltage. To address this limitation, a graded AlGaN/GaN heterostructure is introduced to extend the 2DEG channel into a quasi-three-dimensional electron slab. By comparing the fixed Al composition AlGaN/GaN SBD, Jr of the graded AlGaN/GaN SBD is significantly reduced due to the extension of channel carriers, confirming the effective Jr suppression effect of this structure. Furthermore, on this basis, a recessed anode structure is utilized to expect a smaller Jr. The results indicated that the graded AlGaN/GaN SBDs with air-bridge structure have achieved a pretty low Jr value (1.6 × 10−13 A at -15 V), and its cutoff frequency is as high as 60.6 GHz. It is expected that such SBDs with low Jr have significant advantages in future applications.

Detection of individual spin species via frequency-modulated charge pumping.

We utilize a frequency-modulated charge pumping methodology to measure quickly and conveniently single "charge per cycle" in highly scaled Si/SiO2 metal-oxide-semiconductor field effect transistors. This is indicative of detection and manipulation of a single interface trap spin species located at the boundary between the SiO2 gate dielectric and Si substrate (almost certainly a Pb type center). This demonstration in sub-micrometer devices in which Dennard scaling of the gate oxide has yielded extremely large gate oxide leakage currents eliminates interference between the charge pumping current and the leakage phenomenon. The result is the ability to measure single trap charge pumping reliably and easily, which would otherwise be completely inaccessible due to oxide leakage. This work provides a unique and readily available avenue for single spin species detection and manipulation, which can be applied as a quantized standard of electrical current as well as to serve as a potentially useful platform for developing quantum engineering technologies. Finally, we discuss potential underlying physical mechanisms that are involved in producing a seemingly contradictory measure of both odd and even integer values for charge per cycle.

Three‐phase transformerless photovoltaic inverter without common mode leakage current

AbstractSince three‐phase transformerless (TPT) PV inverters have large common mode leakage current (CMLC), a TPT PV inverter without CMLC is proposed. The proposed inverter is derived from three single‐phase half‐bridge inverters and a boost converter. Grounds of the PV array and three‐phase loads are connected directly, so no CMLC exists in the TPT solar inverter. Operating principle, stability analysis, and loss calculation and example of the proposed three‐phase inverter are illustrated in detail. The pulse‐width modulation (PWM) and sinusoidal PWM control methods are used in the boost converter and three‐phase inverter, respectively. The proposed inverter is a stable system. Finally, simulation and experimental results of a 900‐W TPT PV inverter confirm the theoretical analysis. The CMLC in the proposed inverter is only about 0.8 mA, which is mainly caused by the ground line inductance and oscilloscope probe noise.

Ultra-high energy storage density of transparent capacitors based on linear dielectric ZrO2 thin films with the thickness scaled up to hundreds nanometers

In this work, a high energy storage density in transparent capacitors, based on linear dielectric ZrO2 thin films, with thickness scaled up to hundreds of nanometers, is reported. Linear dielectric ZrO2 films with a thickness of several hundred nanometers are grown on Sn-doped In2O3 (ITO) electrode layers grown on transparent glass substrates at room temperature. The fabricated ITO/ZrO2/ITO capacitors show excellent dielectric energy storage performance, including a large dielectric constant, low loss and leakage current, and large breakdown strength. Consequently, these capacitors present high energy density and efficiency, as well as robust device endurance. In particular, ultra-high recoverable energy storage density (Wrec ∼ 75.4 J/cm3) and efficiency (η ∼ 88%) are achieved simultaneously in ZrO2 film-based (470 nm thick) capacitors, rivaling those of other lead-free ferroelectric-like and other linear dielectric film capacitors. Moreover, the capacitors show good transparency in the visible range, indicating the potential energy-storage applications in transparent electronics.

P-GaN field plate for low leakage current in lateral GaN Schottky barrier diodes

High-voltage gallium nitride Schottky barrier diodes (SBDs) suffer from large off-state leakage current, which further degrades during operation at high temperatures and limits the device blocking capabilities. The key to achieving low off-state leakage is to protect the Schottky barrier from the high electric field, which is challenging by employing conventional field plate structures due to their large pinch-off voltage. In this work, we propose a simple AlGaN/GaN SBD architecture based on a p-GaN cap layer to achieve excellent off-state performance with a very low leakage current. By properly designing the AlGaN barrier and p-GaN cap, the pinch off-voltage of the p-GaN field plate is carefully controlled and the voltage drop over the Schottky junction is effectively reduced. In addition, a large carrier concentration in the access region is achieved, leading to a reduced sheet resistance. This results in good on-state performance along with a very low leakage current of ∼1 nA/mm at 400 V, which is maintained well below 100 nA/mm up to elevated temperatures of 150 °C. Moreover, the proposed architecture shares the well-established fabrication process of commercial p-GaN HEMTs and, thus, represents a promising and viable solution for future GaN diodes.

Polarization-induced internal electric field to manipulate piezo-photocatalytic and ferro-photoelectrochemical performance in bismuth ferrite nanofibers

Developing lead-free ferroelectrics BiFeO3 with polarized electric field for tuning charge-transport properties in piezo-photocatalytic and ferro-photoelectrochemical (PEC) is highly desired but also challenging, especially defects such as impurity phases and oxygen vacancies lead to the weak polarization and large leakage current of BiFeO3. Here, we used a facile electrospinning strategy to modify BiFeO3 nanofibers by A-site Pr ion and B-site Mn ion co-doping. In this way, the concentrations of oxygen vacancies and valence of Fe3+ to Fe2+ were significantly inhibited, and the morphotropic phase boundary (MPB) of the rhombohedral (R) to tetragonal (T) phase was obtained, resulting in better ferroelectric performances and lower leakage current. Thus, BiPrFeMnO3 nanofibers was able to generate a large piezoelectric potential through magnetic stirring (piezoelectric effect) and light irradiation (photocatalytic effect), resulting in superior piezo-photocatalytic performance with a degradation rate of 0.1352 min−1 for rhodamine B, which was 8.29, 4.3 and 4.2 times higher than that of BiFeO3, BiPrFeO3 and BiFeMnO3, respectively. In addition, optimized PEC performance by controlling the polarization state was observed in BiPrFeMnO3. The photocurrent could be effectively tuned by more than 16 times (8.2 −131.2 μA·cm−2 at 0 V vs Ag/AgCl) under irradiation of simulated sunlight by tuning the poling voltage between + 4 and − 4 V. Meanwhile, the onset potential switched from − 0.16 to − 0.18 V, which was favorable for the PEC reactions. Our present work gives a clear understanding of the role of ferroelectric polarization and solar energy conversion and provides a way to develop highly efficient piezo-/ferroelectric nanomaterials.

An Investigation for the Negative-Bias Temperature Instability Aware CMOS Logic

Background: Scaling of the dimensions of semiconductor device plays a very important role in the advancement of Very Large-Scale Integration (VLSI) technology. There are many advantages of scaling in VLSI technology such as increment in the speed of the device and less area requirement of the device. Aggressive device scaling causes some limitations in the form of short channel effects which produce large leakage current. Large leakage current harms the characteristics of the device and affects the reliability of the device. Objective: The most important and popular reliability issue in Deep Sub Micron (DSM) regime is Negative- Bias Temperature Instability (NBTI). NBTI effect increases the threshold voltage of p-channel Metal Oxide Semiconductor (PMOS) device over the time and affects the different characteristics of the device. As a result, circuit delay exceeds the design specification and there may be timing violations or logic failure. Different performance parameters are observed under NBTI effect for different logic gates. Methods: This paper presents an impact of NBTI at 22nm Berkeley short-channel IGFET model4 (BSIM4) Predictive Technology Model (PTM) for Complementary Metal Oxide Semiconductor (CMOS) logic gates. Reliability simulations are utilized to evaluate the amount of gradual damage in PMOS device due to NBTI effect. Results : The impact of NBTI degradation is checked for various CMOS logic gates using Mentor Graphics’s Eldo circuit simulator. Output voltage and drain current are reducing over the time under NBTI effect. Conclusion: NBTI degradation increases the threshold voltage of PMOS device over time and affects the different characteristics of the device.

Self‐Powered Photodetector Based on p‐Type CuBi2O4 with Fermi Level Engineering

AbstractSi‐based photodetectors (PDs) have been widely used in human‐machine interaction systems due to their robust optoelectronic properties despite limitations of significant large leakage current. To overcome this drawback, a functional overlayer of p‐type CuBi2O4 (CBO) is deposited on the surface of n‐type Si to build a novel photodetector involving a p–n heterojunction. Such an n‐Si/p‐CBO photodetector shows an ultralow dark current ≈10−11 A with a high photosensitivity up to 1.69 × 104 at zero bias, a strong self‐powered characteristics with a photovoltage near 0.55 V, and a fast rise and decay time around 0.1 and 0.3 ms. With these advantages, the device shows great performance in the optical communication system. The thickness‐dependent performance indicates that the top layer acts as a light‐harvesting semiconductor to generate, separate, and transport photocarriers through the built‐in heterojunction. Band alignment analysis confirms this result and reveals the formation of a type‐II heterojunction at the interface of n‐Si and p‐CBO layers. This work demonstrates an effective strategy to reduce the leakage current and improves the responsivity, detectivity, and response speed of Si‐based self‐powered photodetectors.

Comparative analysis of leakage current suppression capability of forward‐clamped and reverse‐clamped H10 three‐phase inverters

Non-isolated inverters have the disadvantage of large leakage current, which will damage the equipment and personal safety. In order to solve this problem, this paper proposes two H10 three-phase inverter topologies named forward-clamped and reverse-clamped H10 inverters. Each of the topologies is composed of two DC bus switches, a clamping circuit and a traditional three-phase inverter, but the clamping method of these two topologies is different. A general control strategy combining carrier modulation and logic operation for these two topologies are proposed. The control strategy allows the common-mode voltage of these two topologies to vary between one third and two thirds of the DC bus voltage, but the frequency of the common-mode voltage of the reverse-clamped inverter is three times that of the forward-clamped inverter. The loop impedance of the reverse-clamped inverter increases significantly at high frequency, so the leakage current suppression capability is better. Simulation and experiment platforms of the inverter systems are built. The obtained results verify the correctness of the theoretical analysis.

Effect of Schottky barrier height on quantitative analysis of deep-levels in n-type GaN by deep-level transient spectroscopy

Deep-level transient spectroscopy (DLTS) using Schottky barrier diodes (SBDs) is widely used for quantitative analysis of deep levels. This study focuses on the dependence of Schottky barrier height on apparent time constants and concentrations of electron traps in n-type GaN. DLTS using SBDs with various barrier heights was carried out. Experimental data show that large reverse leakage currents due to low barrier heights resulted in underestimation of time constants and concentrations. Theoretical calculations considering the impact of leakage currents reproduced experimental results well. Based on the calculations, we suggest a minimum required barrier height where accurate time constants and concentrations can be evaluated.

(Invited) Recent Progress on Selective Area Regrowth and Doping for Vertical GaN Power Transistors

Wide bandgap semiconductor GaN is a very promising candidate for efficient power conversion applications due to its large bandgap energy and high critical electric field. Vertical GaN power devices grown on bulk substrates are enabling the next-generation power electronics with higher efficiency, higher power density and smaller form factor. However, selective area doping in GaN is far from mature, which is limiting the realization of many advanced GaN power devices such as vertical junction effect transistors (VJFETs), junction barrier Schottky (JBS), superjunction, and junction termination extension (JTE). Epitaxial regrowth or selective area regrowth has been regarded as one of the most promising routes to selective area doping.Currently, the regrown p-n junctions suffer from large leakage currents and premature breakdown. To understand this phenomena, the regrowth experiments were carried out by metalorganic chemical vapor deposition via an etching-then-regrowth process. The etching was performed by inductively coupled plasma (ICP) etching. The regrowth dynamics with different trench widths and depths was revealed, where basal plane and lateral growth modes were identified. It was also found that shallow trenches for selective area regrowth was beneficial for reducing the reverse leakage currents of regrown p-n junctions.The regrowth interface plays a critical role in understating the leakage mechanism of regrown p-n junctions. With developed material characterization techniques, the regrown structures and interface were analyzed in detail. Cathodoluminescence (CL) and secondary electrons (SEs) were used to realize both lateral and vertical dopant profiling at a sub-micron scale [1]. The regrowth interface by dry etching accumulated lots of impurities and charges, contributing to the formation of a p+-n+ tunneling junction. This was further confirmed by the electrostatic potential profile at the regrowth interface using electron holography [2]. This tunneling junction is likely to be the major contributor to the large reverse leakage currents and low breakdown voltages in regrown junctions. To improve the regrowth interface, novel etching technologies were demonstrated. It was found that low-power dry etching significantly reduced the interfacial charges and the reverse leakage currents of regrown p-n junctions [3]. Atomic layer etching (ALE) was also successfully developed for GaN, which uses self-limiting chemical processes, thus removing the damaged layers without inducing further etching damage. The tertiarybutylchloride (TBCl) based in situ etching may serve as an alternative etching method to dry etching with reduced etching damage [4]. In terms of devices, regrown p-n junctions with low leakage currents [3] and the first normally-off VJFETs were demonstrated. Further improvements in selective area regrowth and associated devices can be expected via regrowth optimization and regrowth interface engineering via surface treatments and low-damage etching. These results represent an important step towards realizing selective area doping for GaN power transistors. H. Liu et al., Appl. Phys. Lett., 114, 082102 (2019)S. Alugubelli, et al., Appl. Phys. Lett., 115, 201602 (2019)K. Fu et al., IEEE Electron Device Lett. 40, 1728 (2019)B. Li et al., Appl. Phys. Lett., 115, 162101 (2019)

Si Substrate Effect on Characteristics of Solid State Incandescent Light Emitting Devices

In the solid state light emitting device (LED), the single wavelength light is emitted from the pn junction structure made on a compound semiconductor wafer [1]. A novel solid-state incandescent light emitting device (SSI-LED) that is made from the MOS capacitor with a high-k gate dielectric was reported recently [1-5]. It emits the warm white light based on the principle of thermal excitation of nano-resistors formed from the dielectric breakdown process [2,5]. This kind of device can be used in lighting, on-chip optical interconnect, nonvolatile memories, etc. [6-8]. In this study, authors report the Si substrate effect on the electrical and optical properties of the device before and after the formation of nano-resistors.MOS capacitors made of the ZrHfO high-k dielectric and ITO gate electrode were fabricated on the dilute HF cleaned Si (100) IC and the poly-Si solar wafers. The high-k dielectric layer was sputter deposited on the wafer followed by furnace annealing at >900oC for 3 min in O2. The sputter deposited ITO film was etched into gate electrodes with a HCl:HNO3=3:1 solution. An aluminum film was deposited on the backside of the wafer to form the ohmic contact. The complete sample was annealed at 400oC for 5 min under N2/H2 90%/10%. The capacitance-voltage (C-V) curve was measured with an Agilent 4284 meter based on which the EOT, VFB , Dit , and Qot were calculated. Subsequently, nano-resistors were formed after the dielectric breakdown process. Light emitted from the SSI-LED under a fixed Vg was characterized.Figure 1 shows C-V hysteresis curves of capacitors made on the (a) Si (100) IC wafer and (b) poly-Si solar wafer. They show similar EOT, Qot , and small hysteresis that means very few trapped charges [9]. However, the device on the poly-Si solar wafer has a much larger Dit than that on the Si (100) wafer, i.e., 1.4x1011 cm-2 eV-1 vs. 7.0x1010 cm-2eV-1, which means a larger interface state density in the former [10]. The small bump in the Fig. 1(b) curve corresponds to the existence of interface states [11]. The high interface states are related to the large number of active defects that lead to the large leakage current, large number of low-frequency noises, and low mobility [11]. The textured surface of the solar wafer could be the reason for the large interface states [12].Figure 2 shows the top views of light emission from SSI-LEDs prepared on the (a) Si (100) IC wafer and (b) poly-Si solar wafer at Vg = -20V. The bright dots in Fig. 2 correspond to thermally excited nano-resistors. They were more uniformly distributed in Fig. 2(a) than in Fig. 2(b). Fig. 2(b) shows many large bright dots, which are contributed by closely located nano-resistors [13]. The color difference among dots could be due to the temperature difference [14]. The higher the temperature is, the shorter the light wavelength is. More detailed electrical and optical characteristics on SSI-LEDs will be presented and discussed.1. S. Nakamura, T. Mukai, and M. Senoh, Appl. Phys. Lett., 64(13), 1687 (1994).2. Y. Kuo and C.-C. Lin, Appl. Phys. Lett., 102(3), 031117 (2013).3. Y. Kuo and C.-C. Lin, Electrochem. Solid-State Lett., 2(8), Q59 (2013).4. Y. Kuo and C.-C. Lin, Solid-State Electron., 89, 120 (2013).5. C.-C. Lin and Y. Kuo, Appl. Phys. Lett., 106(12), 121107 (2015).6. Y. Kuo, ECS Trans., 69(12), 23 (2015).7. S. Zhang and Y. Kuo, ECS J. Solid State Sci. Technol., 6(4), Q39 (2017).8. S. Zhang and Y. Kuo, ECS Trans., 75(45), 17 (2017).9. W. L. Leong, P. S. Lee, S. G. Mhaisalkar, T. P. Chen, and A. Dodabalapur, Appl. Phys. Lett., 90(4), 042906 (2007).10. M. Miczek, C. Mizue, T. Hashizume, and B. Adamowicz, J. Appl. Phys., 103(10), 104510 (2008).11. S. Hlali, N. Hizem, L. Militaru, A. Kalboussi, and A. Souifi, Microelectron. Reliab., 75, 154 (2017).12. L. A. Dobrzański, A. Drygala, J. Achiev. Mater. Manuf. Eng., 31(1), 77 (2008).13. A. Shukla and Y. Kuo, 239th ECS Meeting. Abst. 145365 (2021).14. A. Shukla and Y. Kuo, ECS J. Solid State Sci. Technol., 9(6), 065017 (2020). Figure 1

Study of SiO2 Interfacial Layer Growth during Fabrication Process of Ferroelectric HfxZr1−XO2-Based Metal-Ferroelectric Semiconductor

Recently, ferroelectric HfxZr1−xO2 (HZO) thin films have attracted much attention towards high-density and low-power ferroelectric memories such as ferroelectric field-effect transistors (FeFETs) for artificial intelligence (AI). [1] An annealing process at ≥ 300 °C is typically required to form the ferroelectric orthorhombic (O) phase of HZO films. [2, 3] It remains a big issue of an abnormal SiO2 interfacial layer (SiO2-IL) growth at the HZO/Si interface during metal-ferroelectric-semiconductor (MFS) fabrication process. It has been reported that a SiO2-IL growth led to degradation of remanent polarization (2P r) and reliability of MFS capacitors. [4] However, it is unclear how the process conditions of MFS structures, such as an atomic layer deposition (ALD) of HZO films and annealing process, affect the SiO2-IL formation in detail. In this work, we investigated a SiO2-IL growth as a function of the process temperature of ALD and annealing processes and a SiO2-IL growth of TiN/HZO/Si structures.P+-Si substrate was first cleaned using a buffered hydrofluoric acid to remove native oxide, and then an HZO film was deposited by ALD using H2O gas and (Hf/Zr)[N(C2H5)CH3]4 (Hf:Zr = 1:1) cocktail precursor. The ALD growth temperature was varied from 200 to 300 °C. A 100-nm-thick TiN film was then fabricated as gate electrode by DC sputtering. Finally, the post-metallization annealing (PMA) was carried out at 300–600 °C in an N2 atmosphere. A 3-nm-thick HZO film was used to evaluate the SiO2-IL growth using XPS analysis. On the other hand, TiN-gated MFS capacitor with a 10-nm-thick HZO film was prepared to examine electrical properties.First, the formation of the SiO2-IL was found to be negligible small at HZO (3 nm)/Si interface regardless of the ALD growth temperatures because no significant peak originating from Si-O bonds was observed in XPS spectra of Si 2p. Therefore, we employed 300 °C as an ALD temperature of HZO films for the fabrication of MFS capacitors. Next, the SiO2-IL growth as a function of PMA temperature was evaluated. The SiO2-IL growth increased as PMA temperature increased from 400 to 600 °C. Therefore, the annealing process at a lower temperature suppressed a SiO2-IL growth for the fabrication of MFS structures.Finally, polarization–electric field (P– E) measurements were conducted to evaluate the ferroelectricity of TiN/HZO (10 nm)/p+-Si MFS capacitors after the PMA process at 300–600 °C. The MFS capacitors after the PMA process at 500 and 600 °C showed breakdown during the P– E measurement due to a large leakage current. The MFS capacitor after the PMA process at 400 °C showed significantly higher 2P r value of 26 µC/cm2 compared to that (7.6 µC/cm2) after the PMA process at 300 °C. This is because the HZO films of the MFS capacitor after the PMA process at 400 °C were crystallized with the ferroelectric O phase while the HZO films had an amorphous-like structure after the PMA process at 300 °C, evaluated by X-ray diffraction (XRD). These experimental results indicated that the PMA temperature significantly affects the growth of the SiO2-IL at the HZO/Si interface while almost no difference was observed between the ALD temperature conditions.This work was partially supported by JSPS KAKENHI (JP18J22998 and JP20H02189).[1] J. Y. Kim et al., APL Mater. 9, 021102 (2021).[2] T. Onaya et al., Microelectron. Eng. 215, 111013 (2019).[3] S. J. Kim, et al., S. J. Kim et al., Appl. Phys. Lett. 111, 242901 (2017).[4] J. Mohan et al., Appl. Phys. Lett. 118, 102903 (2021).

Si Substrate Effect on Characteristics of Solid State Incandescent Light Emitting Devices

Solid-state incandescent light emitting devices were fabricated from MOS capacitors with high-k dielectrics on 3 types of silicon substrates, i.e., Si <100>, Si <100> solar, and polycrystalline Si solar wafers, separately. Electrical and optical characteristics of these devices were studied. The MOS capacitor on Si <100> wafer shows the best electrical properties with respect to interface density of states and charge trapping density. After the dielectric breakdown, devices made on solar wafers have larger leakage currents and fewer number of nano-resistors than that made on Si wafer. Grain boundaries of the polycrystalline Si wafer influence the formation of conductive paths and the pattern of light emission. Larger bright dots, which can be contributed by clusters of nano-resistors, were observed on SSI-LEDs made on solar wafers. Therefore, the selection of the substrate is pivotal to the property and application of the SSI-LED.

Leakage current characteristics and ageing assessment technology of roof arrester under ultra harmonics overvoltage

The large leakage current of the roof arrester caused by the high-frequency resonant overvoltage on the high-speed train occurs intermittently, which will cause the arrester to overheat locally. In this work, the overheating issue of the arrester under Ultra Harmonics Overvoltage is studied. Then, the relationship between the active power and the voltage (including amplitude and frequency) of the arrester is investigated, and the impact mechanism of the harmonic voltage on the overheating fault of the arrester is analysed based on experiments in this work. It is found that the total leakage current of the arrester is proportional to the amplitude and frequency of the applied voltage. The internal resistance of the arrester is independent of the amplitude of the voltage, but it will decrease with the increase of the frequency. The main reason that leads to thermal breakdown of the arrester valve under high-frequency harmonic voltage is the heating power elevation of the arrester valve. The research study can provide theoretical basis and data support for the design, type selection and monitoring of the high-speed train roof arrester.

Excellent thermal stability and enhanced piezoelectric performance of Bi(Ni2/3Nb1/3)O3‐modified BiFeO3–BaTiO3 ceramics

AbstractLead‐free piezoelectric ceramics with excellent piezoelectric performance and temperature stability are vital to “stack up” against PZT in various applications. Thus, xBiFeO3‐(1‐x)BaTiO3(BF‐BT)‐based ceramics with high Curie temperatures have drawn increasing attention. However, BF‐BT based ceramics often show large leakage current due to the valence fluctuation of Fe ion. In this work, it is found that Bi(Ni2/3Nb1/3)O3 (BNN) can suppress the valence fluctuation of Fe ions effectively. The effects of BNN on the crystal structure, morphology, and electrical properties of 0.69BF‐0.31BT ceramics are investigated. For composition near morphotropic phase boundary of rhombohedral and tetragonal phases, the Curie temperature (Tc) is as high as 453°C, and the piezoelectric constant (d33), planar electromechanical coupling factor kp, and electric‐field‐induced strain ΔS can reach up to 191 pC/N, 31% and 0.236% (peak to peak), respectively. Moreover, these ceramics show excellent thermal stability. The d33 of 100 pC/N is still maintained at about 360°C and an ultrahigh strain (ΔS = 0.684%, peak to peak strain) is obtained at 190°C. Our work illustrates that the BF‐BT based ceramics can serve as potential candidates for sensor and actuator applications over a broad temperature range.

Mitigating self-discharge of activated carbon-based supercapacitors with hybrid liquid crystal as an electrolyte additive

The application of supercapacitors has been restricted partially due to the high self-discharge rate and large leakage current. In this paper, a nematic hybrid liquid crystal, E7, is adopted as an additive to the electrolyte, and the self-discharge of activated carbon-based supercapacitors is evaluated by tuning various parameters such as initial voltage, current density, temperature and thickness of electrodes. Our results show that the supercapacitors exhibit an obviously lower self-discharge rate due to the contribution of E7, evidenced by the 24 h open circuit potential (OCP) drop from 3 V to 1.4 V with E7, compared to the 24 h OCP drop to 1.1 V in the situation without E7. The leakage current is also reduced from 10 to 2.2 µA with the existence of E7.

Research on the leakage current at sidewall of mesa Ge/Si avalanche photodiode

The effects of surface defects at the sidewall of absorption and multiplication layers on the sidewall leakage current in separate-absorption-charge-multiplication Ge/Si avalanche photodiodes with a mesa structure are investigated. It is found that high-density surface defects and a strong electric field at the sidewall are the reasons for the large sidewall leakage current. In addition, the influence of the width of the guard ring on the sidewall leakage current is also studied. It is found that increasing the width of the guard ring is beneficial to the reduction of the sidewall leakage current by reducing the sidewall electric field and the reduction is not significant when the guard-ring width is greater than 2 µm.

Additional Voltage Loss Considering Jarzynski’s Equality Using Sm-Doped Ceria Electrolytes in Wagner’s Equation for SOFCs

A solid oxide fuel cell (SOFC) directly converts chemical energy from a fuel gas, such as hydrogen or methane, to electrical energy. A solid oxide film is used as the electrolyte, in which the main carriers are oxygen ions. The use of high ion-conducting electrolyte materials, such as samaria-doped ceria (SDC), has been studied to lower the operating temperature. Using SDC electrolytes in solid oxide fuel cells, the open circuit voltage (OCV = 0.80 V at 1073 K) decreases to a smaller value than the Nernst voltage (Vth = 1.15 V at 1073 K), which is obtained using yttria stabilized zirconia (YSZ) electrolytes. This low value has been explained by Wagner’s equation.Based on Wagner’s equation, numerous excellent models have been created. The Riess model is a very famous method for calculating the current-voltage relationship [1]. Using the Riess model, the current-voltage relationship can be calculated with the electrode polarization voltage loss. Furthermore, a nonlinear model was created by Duncan and Wachsman [2]. Using the model described by Duncan and Wachsman, both the electrode polarization voltage loss and the equilibration process can be explained.Previously, we proposed that it is necessary to experimentally verify the existence of leakage currents using Sm-doped Ceria electrolytes in SOFCs. According to the Riess model, the OCV should change during electrode degradation. However, experimentally, the OCV does not change during electrode degradation [3]. Using the model defined by Duncan and Wachsman, the equilibration process that occurs in response to a change in the anode gas for thick Sm-doped ceria electrolytes has never been explained. Experimentally, using a very thick (6.6 mm) SDC electrolyte, the OCV can reach 0.80 V in only 5 minutes [4]. The corresponding electron diffusion current delay should be more than 2080 minutes [5].Next, we proposed an additional voltage loss (0.35 V = 1.15 V- 0.80 V) near the anode [6]. Furthermore, using Jarzynski’s equality, we attempted to explain this voltage loss [7]. The ionic activation energy (Ea) in SDC electrolytes is 0.7 eV. Considering the separation of the Boltzmann distribution during ion hopping by Ea (= 0.7 eV), according to Jarzynski’s equality, the distribution of hopping ions should be a canonical ensemble. When the electrical potential changed due to neutralization by free electrons during ion hopping, 0.7 eV was dissipated by the electrons. Oxygen ions have an electric charge (2e-), so the OCV is 0.8 V= 1.15 V - 0.7 eV/2e [7].Our explanations seem to disregard and disprove Wagner’s equation and other excellent subsequent theories. The reason for this contradiction is that we disproved the existence of large leakage currents in SDC electrolytes. However, we noticed that the dismissal of this idea regarding leakage currents in SDC electrolytes is nothing more than a side effect of introducing a large anode voltage loss (0.35 V). When there is a large voltage loss near the anode in an SDC electrolyte, the leakage currents should be very small. This is called the “anode shielding effect” [8].Our conclusion is that Wagner’s equation becomes more useful after considering the additional voltage loss based on Jarzynski’s equality. Furthermore, subsequent theories such as the Riess model and the Duncan and Wachsman model become more useful. Consequently, it is necessary to introduce new thermodynamics based on Jarzynski’s equality, an addition that will improve Wagner’s equation and subsequent theories.Reference:[1] I. Riess, J. Phys. Chem. Solids., 47(2), 129 (1986). doi: 10.1016/0022-3697(86)90121-6.[2] K. L. Duncan and E. D. Wachsman, J. Electrochem. Soc., 156, B1030 (2009). doi:10.1149/1.315851.[3] T. Miyashita, J. Mater. Sci., 41(10), 3183 (2006). doi: 10.1007/s10853-006-6371-8.[4] T. Miyashita, J. Electrochem. Soc., 164(11) 3190 (2017). doi: 10.1149/2.0251711jes[5] J. Liu and W. Weppner, Ionics, 5(1–2), 115 (1999). doi: 10.1007/BF02375914.[6] T. Miyashita, J. Mater. Sci., 40(22), 6027 (2005). doi: 10.1007/s10855-005-4560-2.[7] T. Miyashita, Miyashita, ECSarXiv (2020) “Open-Circuit Voltage Anomalies in Yttria-Stabilized Zirconia and Samaria-Doped Ceria Bilayered Electrolytes”, https://ecsarxiv.org/xhn73/ [8] B. Dalslet, P. Blennow, P. V. Hendriksen, N. Bonanos, D. Lybye, and M. Mogensen, J. Solid State Electrochem., 10(8), 547 (2006). doi: 10.1007/s10008-006-0135-x.

Electrical and Optical Characteristics of WOx, ZrHfO, and Tri-Layer WOx Embedded ZrHfO High-k Based SSI-LEDs

Three kinds of solid-state incandescent light emitting devices were fabricated from MOS capacitors with gate dielectrics compared of WOx, ZrHfO, and tri-layer WOx embedded ZrHfO, separately. Their electrical and optical characteristics were investigated. The ZrHfO SSI-LED has uniform light emission pattern due to the superb dielectric properties. The WOx SSI-LED showed the highest intensity of emitted light but a large leakage current. The tri-layer WOx embedded ZrHfO SSI-LED has the higher emitted light intensity than the ZrHfO SSI-LED has and a lower leakage current than the WOx SSI-LED has. Therefore, the tri-layer WOx embedded ZrHfO SSI-LED is the preferred device judged from the light emission efficiency and reliability.