Large Integration Circuits Research Articles

(Digital Presentation) Internal Friction, Mechanical Spectroscopy in SiO2/Si Wafers

Introduction The electrophysical properties of semiconductor devices significantly depend on the perfection of their structure. It is necessary to control the structure of semiconductor wafer-plates disks in the manufacture of large integrated circuits (LIC). Technique was developed and device was made that allows to obtain the information about structural defects in such disks by attenuating elastic oscillations Q-1 to study the defects density nd and the depth hd of their propagation. Defect annealing leads to change in the shape of internal friction (IF) temperature spectrum Q-1(T) [1]. IF method allows to set the spectrum of structural defects on the analysis of positions of maximums IF, on duration of relaxation time τ and on their deposit in attenuation of elastic vibrations [2]. A non-destructive method for the technological control of the structure defects by measuring internal friction (IF) and elastic modulus E after laser radiation was developed. Experimental procedure Ultrasonic (US) pulse-phase method using USMV-LETI, modernized USMV-KNU and computerized “KERN-4” with frequencies f║ ≈ 1 MHz and f┴ ≈ 0,7 MHz, US invariant-polarization method for determining the effective acoustic μil and elastic constants Cijkl were used [3,4,5]. The measured velocity error was equal to ΔV/V = 0.5÷1,5%. The study of influence of structure defects on damping of vibrations in Si/SiO2 wafer-plates by the diameter of D = 100÷60 mm and by the thickness of hSiO2 ≈ 600 nm, hSi ≈ 470 000 nm, allows to estimate the degree of perfection of crystalline structure. Metallography optical supervision of microstructure by means of the microscope ”LOMO MVT”, atomic-force microscopy (AFM) were used. Results and discussion The quasi-longitudinal US velocity V║[001] = 5870 m/s, elastic modulus E001 = ρV║[001] 2 = 80,28 GPa for SiO2/Si from the oscillogram were determined. Temperature dependence of internal friction Q-1(T) in SiO2/Si wafer-plate p-type, doped with B, KDB-7.5(100) diameter D ≈ 76∙10-3 m, thickness hSi ≈ 460∙103 nm with SiO2 layer thickness hSiO2 ≈ 100 nm after X-ray irradiation with dose Dγ ≈ 102 Gy is showed. Conclusions It was found that as the result of the structural defect annealing IF background Q0 -1 significantly decreases during measuring of IF temperature dependence Q-1(T), which indicates the improvement of SiO2/Si crystal structure.The elastic modulus Е, the shear modulus G, Poisson coefficient μ, IF Q-1 are dependent from SiO2/Si wafer-plate anisotropy.The value of IF background Q-1 0 after temperature T, mechanical treatments describes the changes of the elastic stress σi fields in SiO2/Si wafer-plate.The study of vibrations of disk wafer-plate Si/SiO2 at different harmonic frequencies f0, f2 made it possible to develop the technique for determining the structural defects density nD for semiconductor wafers-substrates.The relationship between IF Q-1 value, the logarithmic decrement of ultrasound damping δ and the dislocations density nD was established for disk-shaped semiconductor wafers-substrates. Acknowledgements This work has been supported by Ministry of Education and Science of Ukraine: Grant of the Ministry of Education and Science of Ukraine for perspective development of a scientific direction "Mathematical sciences and natural sciences" at Taras Shevchenko National University of Kyiv.

ВИДИ НЕСПРАВНОСТЕЙ МІКРОПРОЦЕСОРНИХ ВЕЛИКИХ ІНТЕГРАЛЬНИХ СХЕМ І УМОВИ ЇХ ПРОЯВУ З УРАХУВАННЯМ ЕНЕРГОДИНАМІЧНОГО ПРОЦЕСУ

The article deals with a mathematical model of microprocessor-based large integrated circuits for monitoring the technical condition, taking into account the energy-dynamic process of this class of microelectronic products, and analyzes typical faults and conditions of their manifestation. The current stage of development of the radioelectronic equipment of the Armed Forces of Ukraine is characterized by the widespread introduction of devices and systems that use large integrated circuits and microprocessor-based large integrated circuits. This is due to the need to process information at a fairly low cost of equipment. When using digital devices with sets of microprocessor-based large integrated circuits, the issue of monitoring the performance and detection of defects in such devices is acute. To improve new methods of diagnosing digital devices, it is necessary to analyze the types of faults that occur in microprocessor-based large integrated circuits. A chip will function properly if it is determined that all instruction sequences are executed correctly under various combinations of data. Complete verification of all instructions executed by a microprocessor-based large integrated circuit is not possible due to the very long length of the tests used for verification. Therefore, to provide test control of the performance of microprocessor-based large integrated circuits, it is necessary to build tests based on a given set of defects, reliability, and time to decision. The analysis of physical processes in logic elements manufactured using the metal-dielectric-semiconductor technology showed that the presence of existing defects leads to the absence of distortion of the quasi-short-circuit current pulse and the output response. That is, the condition for the manifestation of the defect is fulfilled and the diagnostic time is reduced.

SELF-DIAGNOSIS AS A WAY TO INCREASE THE CYBER RESISTANCE OF TERMINAL COMPONENTS OF A TECHNOLOGICAL SYSTEM

The article proposes an approach to determine the technical condition of the terminal components of the technological system, the basis of which are microprocessor systems implemented on software-reconfigurable logic. The existing methods and methods of testing programmable logic integrated circuits are analyzed, the shortcomings and advantages are revealed. It has been proven that the most effective method of using self-diagnosis schemes is BIST — Built-Inself-Test, which in the future can become the basis for monitoring and diagnosing microprocessor systems implemented on a software-reconfigurable element base. The existing methods of determining the technical condition of microprocessor systems implemented on large/very large integrated circuits with rigid architecture are considered, and the mathematical basis of their technical diagnosis is presented. In order to increase the cyber resistance of the terminal components of the technological system, it is proposed to use programmable logic integrated circuits as an element base, which are able to change the internal algorithmic structure by reprogramming as a result of cyber incidents and cyber attacks. At the same time, the reconfiguration of the algorithmic structure of the microprocessor system on the basis of program-reconfigurable logic is proposed to be carried out based on the results of self-diagnosis, that is, by using a diagnostic system with elements of artificial intelligence, which implements the BIST — Built-Inself-Test method. It is assumed that the synergy of the microprocessor system and the diagnostic system with elements of artificial intelligence will allow the implementation of the principle of active fault tolerance (cyber resilience), which consists in the detection and localization of malfunctions (response to cyber incidents and cyber attacks), as well as the restoration of the correct functioning of the terminal components of the technological system by reconfiguring their internal algorithmic structure according to the results of self-diagnosis.

Migrating Assertions From Dense to Discrete Time

Mixed-signal assertions need to be monitored over dense time during analog simulation because analog events are not aligned with clock boundaries in general. On the other hand, simulation of large integrated circuits regularly employs clocked approximations to accelerate the simulation of the analog content in the design. Migrating the analog assertions from the continuous setting to the discrete setting is necessary to monitor compliance in the digital–analog boundary, but such migration must ensure that assertion failures are not missed due to the loss in precision. We propose the formal basis for this migration and a methodology for choosing the granularity of the clock for an assertion in the digital setting.

Dielectric and leakage characteristics of MTO/STO bilayer films deposited by R.F. magnetron sputtering technique for optical and electronic applications

Growth of MgTiO3 (MTO) film on SrTiO3 (STO) coated substrate of three different thicknesses (abbreviations: STMT1, STMT2 and STMT3) by R.F. sputtering technique, and their optical, dielectric and electrical responses have been reported. The XRD analysis revealed polycrystallinity and lattice strain. The STMT bilayers showed MTO thickness dependent granular topography. The estimated optical band gaps are found to be in the range of 3.735–3.727 eV. The dielectric constant showed inverse dependency with MTO thickness, and remained almost invariant with temperature (303–350 K). Impedance analysis established a correlation with the microstructures. The leakage current (J = 10−6 A/cm2 for E = 200 kV/cm) analysis revealed: Schottky conduction and space charge limited mechanism conduction in the lower and higher field regions, respectively. The slope of C vs. V is found to be 259 µF/V. The obtained characteristics of STMT bilayers are potential candidates for large band gap optical and electronic integrated circuit applications.

ЧАСТОТНИЙ АНАЛІЗ СИГНАЛІВ ПРИ ДІАГНОСТУВАННІ ЦИФРОВИХ ТЕЗ ЕНЕРГОДИНАМІЧНИМ МЕТОДОМ

The article analyzes the type of energy-dynamic pulses in the space-time and frequency-spectral domains to improve the diagnostic process of digital standard replacement elementswith large integrated circuits and microprocessor-based large integrated circuits in their design.Creation of new and improvement of existing systems used to determine the technical condition of digital devices in complex conditions requires the development of new methods of diagnosis. This is due to the high complexity of radio-electronic equipment and the shortage of decision time when carrying out technical state control.In the scientific and technical literature on the development and operation of radio electronic equipment, the main attention is paid to the study of the possibility of minimizing the average recovery time and cost of means of diagnostics of the radio electronic equipment object.The main factor holding back the development of modern technical diagnosis systems is the lack of a methodological apparatus capable of significantly more effective use of developed diagnostic models to identify faulty logical elements. Application of the proposed scientific approaches to the processing of diagnostic information will allow: to determine in advance the elements whose characteristics are approaching critical; to determine the technical condition of radio electronic equipment in real time; to monitor the serviceability of elements of radio electronic equipment.It will also allow for more accurate processing of diagnostic parameter values, forecasting failure times of radio electronic components with a given reliability.This, in its turn, will lead to decrease of detection time of sudden failures of radio-electronic facilities and considerably reduce time spent on restoration of digital standard replacement elements of radio-electronic equipment, requirements to which are constantly growing in conditions of repulsion of the russian aggression by the Armed Forces of Ukraine.

Deep learning-based image analysis framework for hardware assurance of digital integrated circuits

We propose a complete Artificial Intelligence (AI)/Deep Learning (DL)-based image analysis framework for hardware assurance of digital integrated circuits (ICs). Our aim is to examine and verify various hardware information by analyzing the Scanning Electron Microscope (SEM) images of an IC. In our proposed framework, we make use of DL-based methods at all essential steps of the analysis. To the best of our knowledge, this is the first such framework that makes heavy use of DL-based methods at all essential analysis steps. For image analysis tasks such as stitching misalignment detection and stacking movement regression that were previously performed mainly manually, we propose novel DL-based method and novel DL model architecture to automate these tasks. One of the salient features of our proposed framework is the heavy use of automated and semi-automated methods in preparing training data and the use of synthetic data to train a DL model. We also propose to train a preliminary DL model for training data preparation in scenarios where the noise level of the image set is high. Further, to maximally encourage model re-use, we propose various DL models that can operate on feature images thus applicable to new image sets without model re-training. By applying our proposed framework to analyzing a set of SEM images of a large digital IC, we prove its efficacy. Our DL-based methods are fast, accurate, robust against noise, and can automate tasks that were previously performed mainly manually. Overall, we show that, by applying our proposed various DL-based methods, we can largely increase the level of automation in hardware assurance of digital ICs and improve its accuracy.

Statistically inspired multi-shift Arnoldi projection for on-chip interconnects

Model order reduction of electronic devices and on-chip interconnects plays an important role in determining the performance of very large scale IC (Integrated Circuit) designs. The ever shrinking process technology continues to increase complexity of these systems with the current Intel device technology node standing at 10 nm. In the analysis of high-speed IC interconnects, the reduced model is often required to approximate the original system in the desired frequency range. In this paper, an efficient Statistically Inspired Multi-shift Arnoldi (SIMA) Method is proposed, which dynamically selects normally distributed shifts to determine the projection matrix. The SIMA is implemented by developing an iterative algorithm for approximation of large-scale systems as an eigenvalue problem using statistically generated interpolation points. The motivation of selecting these points weighted with the Gaussian kernel is derived from the fact that there exist many natural phenomenon, which follow normal distribution. Simulation results have shown better accuracy for the proposed method as compared to other existing model order reduction techniques.

Polarization-Insensitive Waveguide Schottky Photodetectors Based on Mode Hybridization Effects in Asymmetric Plasmonic Waveguides.

Two types of configurations are theoretically proposed to achieve high responsivity polarization-insensitive waveguide Schottky photodetectors, i.e., a dual-layer structure for 1.55 µm and a single-layer structure for 2 µm wavelength band. Mode hybridization effects between quasi-TM modes and sab1 modes in plasmonic waveguides are first presented and further investigated under diverse metal types with different thicknesses in this work. By utilizing the mode hybridization effects between quasi-TE mode and aab0 mode, and also quasi-TM and sab1 mode in our proposed hybrid plasmonic waveguide, light absorption enhancement can be achieved under both TE and TM incidence within ultrathin and short metal stripes, thus resulting in a considerable responsivity for Si-based sub-bandgap photodetection. For 1.55 µm wavelength, the Au-6 nm-thick device can achieve absorptance of 99.6%/87.6% and responsivity of 138 mA·W−1/121.2 mA·W−1 under TE/TM incidence. Meanwhile, the Au-5 nm-thick device can achieve absorptance of 98.4%/90.2% and responsivity of 89 mA·W−1/81.7 mA·W−1 under TE/TM incidence in 2 µm wavelength band. The ultra-compact polarization-insensitive waveguide Schottky photodetectors may have promising applications in large scale all-Si photonic integrated circuits for high-speed optical communication.

ПОДХОД К КОДИРОВАНИЮРЕШЕНИЙ В ЭВОЛЮЦИОННЫХ МЕТОДАХ ДЛЯ СОЗДАНИЯИНСТРУМЕНТАЛЬНОЙ ПЛАТФОРМЫ ПРОЕКТИРОВАНИЯ

The article considers current issues and analyzes the problems of three-dimensional integrationand three-dimensional modeling that arise at the design stage during the solution of theproblem of optimal planning of components of large and extra-large integrated circuits and casedevices of electronic computing equipment. The main advantages of applying the principles ofthree-dimensional integration are presented and described in sufficient detail, which allow efficientlyorganizing the production of personalized electronics, optimally planning the configurationof large and ultra-large integrated circuits, taking into account thermal and energy characteristics.In the course of research, the authors developed an approach to encoding decisions based onan intelligent mechanism, which is characterized by the presence of built-in means of control ofacceptable decisions. One of such tools that have experimentally proven their effectiveness is thebuilt-in mechanism of “deadly mutations”, which takes into account the status of genes and predeterminedrestrictions on the final configuration of the housing of the designed device. A series ofgeneral approaches and specific algorithms for solving the planning problem based on the resultsof research by the author's team and modern approaches to solving NP-complete problems areproposed. The most important practically significant result of the research of the indicated problemis the developed software and instrumental design platform in the modern cross-platform Javaprogramming language. The selected development technology allows you to use all the main advantagesof modern multi-core and multi-processor architectures, to use software multi-threadingto implement parallel schemes for solving combinatorial problems. The software and tool platformhas a user-friendly interface, which allows you to effectively manage the process of solving theproblem of planning the components of large and ultra-large integrated circuits of threedimensionalintegration by visualizing key performance indicators of algorithms on graphs and intext statistics blocks. The developed application software made it possible to carry out a series ofcomputational experiments based on random data sets, as well as on open-data boron benchmarksfor such tasks. The results of experimental studies have confirmed the theoretical estimates of thetime complexity and effectiveness of the proposed approaches and algorithms, including the geneticalgorithm, which uses the new decision coding mechanism proposed in the work.

Silicon photonics co-integrated with silicon nitride for optical phased arrays

In the current work we present Si and SiN combined photonic built-up for optical phased arrays (OPAs) and other large area photonic integrated circuits. We report low-loss co-integrated SiN waveguides and nearly lossless vertical transitions between Si and SiN layers, as well as efficient Si thermo-optical phase shifter module. OPA consisting of 64 optical antennas forming highly collimated beam with 0.4° × 0.47° divergence is reported. By changing input wavelength, solid-state beam steering of 0°–10° is achieved.

Design and Implementation of Ternary Logic Integrated Circuits by Using Novel Two-Dimensional Materials

With the approaching end of Moore’s Law (that the number of transistors in a dense integrated circuit doubles every two years), the logic data density in modern binary digital integrated circuits can hardly be further improved due to the physical limitation. In this aspect, ternary logic (0, 1, 2) is a promising substitute to binary (0, 1) because of its higher number of logic states. In this work, we carry out a systematical study on the emerging two-dimensional (2D) materials (MoS2 and Black Phosphorus)-based ternary logic from individual ternary logic devices to large scale ternary integrated circuits. Various ternary logic devices, including the standard ternary inverter (STI), negative ternary inverter (NTI), positive ternary inverter (PTI) and especially the ternary decrement cycling inverter (DCI), have been successfully implemented using the 2D materials. Then, by taking advantage of the optimized ternary adder algorithm and the novel ternary cycling inverter, we design a novel ternary ripple-carry adder with great circuitry simplicity. Our design shows about a 50% reduction in the required number of transistors compared to the existing ternary technology. This work paves a new way for the ternary integrated circuits design, and shows potential to fulfill higher logic data density and a smaller chip area in the future.

Digital Equalization With ADC-Based Receivers: Two Important Roles Played by Digital Signal Processingin Designing Analog-to-Digital-Converter-Based Wireline Communication Receivers

Wireline input/output (I/O) bandwidth demand within networks in large data centers has increased rapidly over the last decade because of the explosion in data generation from cloud computing, mobile devices, and Internet of Things applications. To support this, both the number of I/O lanes per component and the per-lane data rate have continuously scaled up. For example, Figure 1 shows that the aggregate bandwidth of a typical large Ethernet switch application-specified integrated circuit (IC) has increased by an order of magnitude roughly every five years, starting at about 240 Gb/s with 24 channels operating at 10 Gb/s in 2008 and projected to near 25.6 Tb/s with 256 channels operating close to 100 Gb/s in 2019 [1]. This has led to the development of the current serial I/O standards at 56 Gb/s and planned future links operating in excess of 100 Gb/s.

Hybrid importance sampling Monte Carlo approach for yield estimation in circuit design

The dimension of transistors shrinks with each new technology developed in the semiconductor industry. The extreme scaling of transistors introduces important statistical variations in their process parameters. A large digital integrated circuit consists of a very large number (in millions or billions) of transistors, and therefore the number of statistical parameters may become very large if mismatch variations are modeled. The parametric variations often cause to the circuit performance degradation. Such degradation can lead to a circuit failure that directly affects the yield of the producing company and its fame for reliable products. As a consequence, the failure probability of a circuit must be estimated accurately enough. In this paper, we consider the Importance Sampling Monte Carlo method as a reference probability estimator for estimating tail probabilities. We propose a Hybrid ISMC approach for dealing with circuits having a large number of input parameters and provide a fast estimation of the probability. In the Hybrid approach, we replace the expensive to use circuit model by its cheap surrogate for most of the simulations. The expensive circuit model is used only for getting the training sets (to fit the surrogates) and near to the failure threshold for reducing the bias introduced by the replacement.

VeriIntel2C: Abstracting RTL to C to maximize High-Level Synthesis Design Space Exploration

The design of integrated circuits (ICs) is typically done using low level Hardware Description Languages (HDLs) like Verilog or VHDL (Register Transfer Level). These enable the full controllability of the generated hardware design as they allow to specify the detailed behaviour and structure of the architecture, at every single clock cycle. The main drawback of using these low level HDLs is that takes very long time to create and verify large ICs with them. Moreover, it is hard to re-use HDL code for future projects that require changes in the micro-architecture. Thus, the industry is moving the level of abstraction to C-based VLSI design where designers only have to specify the functionality of the program and High-Level Synthesis (HLS) tools generate the HDL automatically. One additional benefit of C-based VLSI design is that it enables to explore the search space of possible micro-architectures from a single behavioral description. The result of a Design Space Exploration (DSE) is a trade-off curve of Pareto-optimal designs with unique area vs. performance metrics. Most VLSI design companies have large amounts of legacy HDL code. Thus, it makes sense to have an automatic flow to convert HDL designs into behavioral descriptions (e.g. C, C++ or SystemC) optimized for HLS DSE. This implies that the generation of explorable constructs, e.g. loops and arrays, which upon exploration, lead to very different micro-architectures (e.g. loops can be unrolled or folded, arrays can be mapped to RAMs or registers).In this paper, we propose a robust RTL to C translation method called VeriIntel2C to abstract RTL descriptions (written in Verilog) into ANSI-C descriptions optimized for HLS DSE by generating a large number of loops and arrays. Our method is able to generate these explorable constructs with the use of extended Hardware Petri Nets to extract the behaviour of the Verilog designs and to generate a Control Data Flow Graph (CDFG) that allows the easy identification of these constructs. From the experimental results, we are able to demonstrate that VeriIntel2C expands the design space considerably and also improves the quality of design space by 55% on average compared to previous work, on a wide range of designs.

Large Scale Parallel DNA Detection by 2D Solid-State Multi-pore System

We propose a new scalable device design based on the use of nanoscale semiconductor materials to detect and identify translocations of many biomolecules in a massively parallel detection scheme. These devices hold the potential for utilization in the risk assessment of early diagnosis as well as seamless integration with semiconductor electronics. In our scenario, DNA molecules are treaded through nanopores drilled in electrically active two-dimensional graphene to be sensed by the changes produced on an electronic current flowing through the membrane. We use molecular dynamics coupled to nanoscale device simulations to explore the ability of this device setup to uniquely recognize parallel DNA translocation. In particular, we show that electronic sensing offers a higher detection resolution compared to ionic current blocking technique, since simultaneous translocation of DNA through multiple pores can result in crosstalk between the ionic currents while transverse sheet currents are sufficiently insulated due to their ability to sense the local potential changes only. Our device design paves the way towards developing large scale solid-state biomolecular integrated circuits (ICs) with differential control over individual pore sensing geometries as well as detection sensitivities.

Asymmetry dual-LFSR reseeding for low power BIST

Growing test data volume and excessive test power consumption are two of the major concerns for the industry when testing large integrated circuits. LFSR-decompressor-based compression methods have been widely adopted to reduce test data volume because they can provide high compression ratio. These techniques have been enhanced to address the need for low power as well as low test data volume. The key idea behind these methods is to generate seeds for LFSR reseeding such that the don’t-cares in test cubes are filled with proper values to reduce the transition count. This paper presents a LFSR reseeding approach adopting dual-LFSR to effectively reduce the amount of test data while keeping the scan-in power as low. Two LFSRs are used to jointly generate test patterns for a given test set to increase the correlation between neighboring bits and thus to reduce the transition count. Experimental results on the ISCAS’89 benchmarks demonstrate that our proposed approach can achieve a better compression ratio than the existing related dual-LFSR scheme while keeping a roughly equal shifting power reduction.

4H-SiC Pseudo-CMOS Logic Inverters for Harsh Environment Electronics

For logic gate with higher voltage swing, 4H-SiC pseudo-CMOS logic inverter with four nMOS was suggested and demonstrated, and a high voltage swing of 4.4 V was achieved at VDD=5 V. Simple nMOS inverters were also investigated. Both of pseudo-CMOS and nMOS inverters were operated at a high temperature of 200°C. For future SiC large integrated circuits, junction leakage current between n+ regions were also investigated with the comb-shaped test elements.

A Practical Logic Obfuscation Technique for Hardware Security

A number of studies of hardware security aim to thwart piracy, overbuilding, and reverse engineering (RE) by obfuscating and/or camouflaging. However, these techniques incur high overheads, and integrated circuit (IC) camouflaging cannot provide any protection for the gate-level netlist of the third party intellectual property (IP) core or the single large monolithic IC. In order to circumvent these weaknesses, this brief elaborately analyzes these hardware security techniques and proposes a practical logic obfuscation method with low overheads to prevent an adversary from RE both the gate-level netlist and the layout-level geometry of IP/IC and protect IP/IC from piracy and overbuilding. Experimental evaluations demonstrate the low area, power, and zero performance overhead of the proposed obfuscation technique.

Trimming the threshold dispersion below 10 e-rms in a large area readout IC working in a single photon counting mode

We present a new method of an in-pixel threshold dispersion correction implemented in a prototype readout integrated circuit (IC) operating in a single photon counting mode. The new threshold correction method was implemented in a readout IC of area 9.6× 14.9 mm2 containing 23552 square pixels with the pitch of 75 μm designed and fabricated in CMOS 130 nm technology. Each pixel of the IC consists of a charge sensitive amplifier, a shaper, two discriminators, two 14-bit counters and a low-area trim DACs for threshold correction. The user can either control the range of the trim DAC globally for all the pixels in the integrated circuit or modify the trim DACs characteristics locally in each pixel independently. Using a simulation tool based on the Monte-Carlo methods, we estimated how much we could improve the offset trimming by increasing the number of bits in the trim DACs or implementing additional bits in a pixel to modify the characteristics of the trim DACs. The measurements of our IC prototype show that it is possible to reduce the effective threshold dispersion in large-area single-photon counting chips below 10 electrons rms.