Large Industrial Designs Research Articles

Statistical Timing Models for Large Macro Cells and IP Blocks Considering Process Variations

Integrated circuits today rely on extensive reuse of IP bocks and macro cells to meet the demand for high performance system-on-chip. We propose a methodology for extracting timing models of IP blocks and macro cells for statistical timing analysis considering process variations and spatial correlations. We develop efficient models for capturing both inter-die and intra-die variations in device and interconnect parameters. Increasing spatial correlations in variability of the process parameters in subnanometer designs requires instance-specific characterization of these design blocks. We propose a novel technique for instance-specific calibration of precharacterized timing model. The proposed approach was evaluated on large industrial designs of 1.2- and 3.5-M gates in 65-nm technology and validated against SPICE for accuracy.

An On-the-Fly Parameter Dimension Reduction Approach to Fast Second-Order Statistical Static Timing Analysis

While first-order statistical static timing analysis (SSTA) techniques enjoy good runtime efficiency desired for tackling large industrial designs, more accurate second-order SSTA techniques have been proposed to improve the analysis accuracy, but at the cost of high computational complexity. Although many sources of variations may impact the circuit performance, considering a large number of inter- and intra-die variations in the traditional SSTA is very challenging. In this paper, we address the analysis complexity brought by high parameter dimensionality in SSTA and propose an accurate yet fast second-order SSTA algorithm based on novel on-the-fly parameter dimension reduction techniques. By developing a reduced rank regression (RRR)-based approach and a method of moments (MOM)-based parameter reduction algorithm within the block-based SSTA flow, we demonstrate that accurate second-order SSTA can be extended to a much higher parameter dimensionality than what is possible before. Our experimental results have shown that the proposed parameter reductions can achieve up to 10times parameter dimension reduction and lead to significantly improved second-order SSTA under a large set of process variations.

An Efficient Unknown Blocking Scheme for Low Control Data Volume and High Observability

This paper presents an efficient method to block unknowns for temporal compactors. The proposed blocking logic can reduce data volume required to control the blocking logic and increase the number of scan cells that are observed by temporal compactors. Control patterns, which specify values required at the control signals of the blocking logic, are compressed by linear feedback shift register reseeding. In this paper, the blocking logic gates for some scan chains that do not capture unknowns are bypassed. Since all scan cells in these scan chains can be observed without specifying the corresponding bits in control patterns, more scan cells are observed while a smaller number of bits are required to be specified. The seed size is further reduced by reducing the numbers of specified bits in the densely specified control patterns. The proposed method can always achieve the same fault coverage that can be achieved by directly observing scan chains without any output compaction. Experiments with large industrial designs clearly demonstrate that the proposed method is scalable to large circuits. Hardware overhead for the proposed unknown blocking scheme is very low.

Advances in Predicate Abstraction

随着软、硬件系统规模和功能的不断扩充,状态空间爆炸问题严重影响了模型检验的进一步发展与应用,成为验证大规模系统的瓶颈.谓词抽象是解决状态空间爆炸的最有效方法之一,近年来得到迅速发展.介绍了谓词抽象的基本算法并比较了不同的求解支持工具;重点分析了反例指导的抽象求精和基于插值的抽象求精原理;分析了产生新谓词的各种方法的优、缺点;最后指出了谓词抽象技术进一步发展所面临的挑战和发展方向.;With the growing increase in software/hardware system scale and function, the further development and application of model checking has been greatly limited by state space explosion, which becomes the bottleneck of verifying large industrial designs. Predicate abstraction, as one of the most effective ways to address state explosion, has been fueled over the recent years. This paper presents a survey of the latest developments in predicate abstraction. A basic algorithm for predicate abstraction is introduced first, followed by comparison among several solvers. Emphases are put on counterexample-guided abstraction refinement and interpolation-based abstraction refinement, including the principles and improvements. The qualities of the new predicate generation methods are also analyzed. Finally, the major challenges in making this technology more pervasive in industrial design verification domain are noted.

A Methodology for Handling Complex Functional Constraints for Large Industrial Designs

Functional constraints capture Boolean relationships among signal nets by analyzing the functionality of a circuit. Such constraints find widespread application in VLSI design methodology and can be derived using various techniques. The size and complexity of these constraints becomes a limiting factor in their successful usage for large designs. This paper describes CONAN (Constraint Analyzer), a powerful framework to analyze and simplify such constraints. CONAN is built on the solution to a novel minimization problem. The feasibility and effectiveness of CONAN is demonstrated by using it for functional untestability analysis of large industrial benchmarks. Run-times were reduced from over a week to less than 30 minutes. Additionally, unique functionally untestable faults were derived using this approach when compared with constraints provided by designers.

RTL-Aware Cycle-Accurate Functional Power Estimation

Most methods for hardware power estimation operate at the register-transfer level (RTL) or lower levels of design abstraction. Since cycle-accurate functional descriptions (CAFDs) are being widely adopted in integrated circuit (IC) design flows, power estimation can potentially benefit from the inherent increase in the efficiency of a cycle-based functional simulation. However, attempts at power estimation for functional descriptions have suffered from a poor accuracy because the design decisions performed during their synthesis lead to an unavoidable large uncertainty in any power estimate that is based solely on the functional description. The authors propose a methodology for a CAFD power estimation that combines the accuracy achieved by structural RTL power estimation with the efficiency of cycle-accurate functional simulation. This goal is achieved by viewing a CAFD as an abstraction of a specific known RTL implementation that is synthesized from it. The authors identify correlations between a CAFD and its RTL implementation and back-annotate information into the CAFD solely for power estimation. The resulting RTL-aware CAFD contains a layer of code that instantiates virtual placeholders for RTL components and maps values of CAFD variables into the RTL components' inputs/outputs, thus enabling efficient and accurate power estimation. Power estimation is performed in the proposed methodology by simply cosimulating the RTL-aware CAFD with a simulatable power-model library that contains power macromodels for each RTL component. Techniques to further improve the speed of CAFD power estimation through the use of control-state-based adaptive power sampling are presented. The authors have implemented and evaluated the proposed techniques in the context of a commercial C-based hardware design flow. Experiments with a number of large industrial designs (up to 1 000 000 gates) demonstrate that the proposed methodology achieves an accuracy very close to RTL power estimation with two-three orders of magnitude speedup in estimation times

A Statistical Quality Model for Delay Testing

SUMMARY In this paper we introduce a statistical quality model fordelay testing that reflects fabrication process quality, design delay margin,and test timing accuracy. The model provides a measure that predicts thechip defect level that cause delay failure, including marginal small delay.We can therefore use the model to make test vectors that are effective interms of both testing cost and chip quality. The results of experiments us-ing ISCAS89 benchmark data and some large industrial design data reflectvarious characteristics of our statistical delay quality model. key words: delay testing, quality model, defect distribution 1. Introduction The progress of fabrication process and design technologyleads to marginal or parametric failures that are caused byresistive shorts or resistive vias [1]. They will occur moreoften and it will be more difficult to screen them effectivelyby the conventional testing methods.Delay testing is regarded as one of the key technologiesfor those problems and has been widely studied to improvetesting effectiveness. Many delay fault models were pro-posed. The transition delay fault model [2] considers thepropagation of lumped delay defects by logical transition tothe observation pins or flip-flops. It is widely used becauseof its high fault coverage, but it cannot detect defects caus-ing delays that are smaller than the test timing. The path de-lay fault model [2] considers the propagation of distributeddelay along a path. It can detect small delay defects, but itis hard to achieve high fault coverage because there is ex-ponential number of paths in a chip. Some longest pathsare selected and tested; however, their coverage is so smallthat the effectiveness is not quantified [2]. A statistical pathselection technique that considers process variation was pro-posed [3]. It is a reasonable approach for practical testing,but its effectiveness is still unknown.There are some papers that address small delay defects.Park et at.[4],[5] give the basic idea that evaluates small de-lay defects. They introduced the delay defect density func-

On modeling crosstalk faults

Traditionally, digital testing of integrated semiconductor circuits has focused on manufacturing defects. There is another class of failures that happens due to circuit marginalities. Circuit-marginality failures are on the rise due to shrinking process geometries, diminishing supply voltage, sharper signal-transition rates, and aggressive styles in circuit design. There are many different marginality issues that may render a circuit nonoperational. Capacitive cross coupling between interconnects is known to be a leading cause for marginality-related failures. In this paper, we present novel techniques to model and prioritize capacitive crosstalk faults. Experimental results are provided to show effectiveness of the proposed modeling technique on large industrial designs.

Distributed CTL model checking

As model checking becomes increasingly used in industry, there is a big need for efficient new methods to deal with the large real-size designs. The author presents a novel method for improving the performance of model checking using parallelisation techniques. The model checking is performed on a distributed-memory environment consisting of a network of machines. The important two keys to focus on are the memory balance and communication reduction. A new algorithm for partitioning the large state space modelling industrial designs with hundreds of millions of states and transitions is proposed. The state space is supposed to be represented by a weighted Kripke structure (this is an extension of the Kripke structure where weights are associated with the states and with the transitions). This algorithm partitions the weighted Kripke structure by performing a combination of abstraction-partition-refinement on this structure. The CTL model checking algorithm is distributed on processes located on different network machines. Each one owns a partition and executes the algorithm on it. The algorithm for CTL model checking is designed to reduce the communication overhead between the processes. The experimental results on large real designs show that this method improves the quality of partitions, the communication overhead and then the overall performance of the model checking.

Extraction of Two-Node Bridges From Large Industrial Circuits

Enumeration and prioritization of highly probable bridges based on the circuit layout and manufacturing defect data is a key step in defect-based testing. Existing solutions either do not scale to large designs or compromise on the accuracy of the computation when applied to very large circuits. This paper presents a scalable and efficient methodology to accurately extract two-node bridges from very large circuits. To our knowledge, this is the first solution to be presented that can process such large industrial designs accurately. It also naturally addresses two important issues viz. through the cell routing and name propagation. Experimental results illustrating key features of the algorithm, including scalability and efficient memory usage, are presented.

Probabilistic analysis of interconnect coupling noise

Noise simulators and noise avoidance tools are playing an increasingly critical role in the design of deep submicron circuits. However, noise estimates produced by these simulators are often very pessimistic. For large, high-performance industrial ICs, which can contain hundreds of thousands of nets, the worst case estimates of the noise results in thousands of reported violations, without any information about the likelihood of the possible noise violation. In this paper, we present a probabilistic approach to prioritize the violating nets based on the likelihood of occurrence of the reported noise. We derive an upper bound on the probability that the total noise injected on a given victim net by a specific set of aggressors exceeds a threshold. This is equivalent to a lower bound on the expected number of clock cycles required to realize the noise violation for the first time, i.e., mean time-to-failure. If the probability of a failure in a victim is sufficiently small, it is possible that even during the operation of the part for a number of years, the probability of failure on the net is negligible and the net can be assigned a lower priority for the application of noise avoidance strategies. We demonstrate the utility of this approach through experiments carried out on an large industrial processor design using a state-of-the-art industrial noise analysis tool.

Design hierarchy-guided multilevel circuit partitioning

In this paper, we present a new multilevel circuit partitioning algorithm (dhml) which is guided by design hierarchy. In addition to flat netlist hypergraph, we use user design hierarchy as a hint for partitioning. This design hierarchy already has some implications on connectivity between logical blocks in the design. Using design hierarchy in partitioning is nontrivial since the hierarchical elements in design hierarchy do not necessarily have strong internal connectivity; hence, we need to determine whether it is preferable to break up or preserve the hierarchical elements. In order to identify and select the hierarchical elements with strong connectivity, their Rent exponents are used. Then, the selected hierarchical elements serve as effective clustering scopes during the multilevel coarsening phase. The scopes are dynamically updated (enlarged) while building up a clustering tree so that the clustering tree resembles the densely connected portions of the design hierarchy. We tested our algorithm on a set of large industrial designs in which the largest one has 1.8 million cells, 2.8 million nets, and 11 levels of hierarchy. By exploiting design hierarchy, our algorithm produces higher quality partitioning results than the state-of-the-art multilevel partitioner hMetis. Furthermore, experimental results show that dhml yields significantly more stable solutions, which is helpful in practice to reduce the number of runs to obtain the best result.

Adaptive delay estimation for partitioning-driven PLD placement

This paper describes the application of weighted partitioning techniques to timing-driven placement on a hierarchical programmable logic device. We discuss the nature of placement on these architectures, the details of applying weighted techniques specifically to the programmable logic device (PLD) CAD flow, and introduce the new concept of adaptive delay estimation using phase local to increase performance. Empirical results show that these techniques, in a fully complete system with large industrial designs, give an average 38.5% improvement over the unimproved partitioning-based placement tool. Approximately two-thirds of this benefit is due to our improvements over a straightforward weighted partitioning approach.

Using word-level ATPG and modular arithmetic constraint-solving techniques for assertion property checking

We present a new approach to checking assertion properties for register-transfer level (RTL) design verification. Our approach combines structural word-level automatic test pattern generation (ATPG) and modular arithmetic constraint-solving techniques to solve the constraints imposed by the target assertion property. Our word-level ATPG and implication technique not only solves the constraints on the control logic, but also propagates the logic implications to the datapath. A novel arithmetic constraint solver based on modular number system is then employed to solve the remaining constraints in datapath. The advantages of the new method are threefold. First, the decision-making process of the word-lever ATPG is confined to the selected control signals only. Therefore, the enumeration of enormous number of choices at the datapath signals is completely avoided. Second, our new implication translation techniques allow word-level logic implication being performed across the boundary of datapath and control logic and, therefore, efficiently cut down the ATPG search space. Third, our arithmetic constraint solver is based on modular instead of integral number systems. It can thus avoid the false-negative effect resulting from the bit-vector value modulation. A prototype system has been built that consists of an industrial front-end hardware description language (HDL) parser, a property-to-constraint converter, and the ATPG/arithmetic constraint-solving engine. The experimental results on some public benchmark and industrial circuits demonstrate the efficiency of our approach and its applicability to large industrial designs.

Verification of Large State/Event Systems Using Compositionality and Dependency Analysis

A state/event model is a concurrent version of Mealy machines used for describing embedded reactive systems. This paper introduces a technique that uses compositionality and dependency analysis to significantly improve the efficiency of symbolic model checking of state/event models. It makes possible automated verification of large industrial designs with the use of only modest resources (less than 5 minutes on a standard PC for a model with 1421 concurrent machines). The results of the paper are being implemented in the next version of the commercial tool visualSTATETM.

A Practical Vector Restoration Technique for Large Sequential Circuits

Given a test sequence and a list of faults detected by the sequence, vector restoration techniques extract a minimal subsequence that detects a chosen subset of modeled faults. Vector restoration techniques are useful in static compaction of test sequences and in fault diagnosis. We propose a new vector restoration technique that is a significant improvement over the state of the art in several ways: (1) a sequence of length n can be restored with only O(n log2n) simulations while known approaches require simulation of O(n2) vectors, (2) a two-step restoration process is used that makes vector restoration practical for large designs, and (3) restoration process for several faults is overlapped to provide significant acceleration in vector restoration. Our new ideas can be used to improve run-times of known static compaction and fault diagnosis methods. We integrated the proposed vector restoration technique into a static test sequence compaction system. Our experiments show that the new restoration technique, as compared to known techniques (Proceedings of Int. Conf. on Computer Design, University of Iowa, Aug. 1997, pp. 360–365.), is (1) about 2 times faster for the ISCAS benchmark circuits, and (2) 3 to 5 times faster on large, industrial designs. Using the new restoration technique, we successfully processed large industrial designs that could not be handled by earlier techniques (Proceedings of Int. Conf. on Computer Design, University of Iowa, Aug. 1997, pp. 360–365.) in 2 CPU days.

A new approach for parallel simulation of VLSI circuits on a transistor level

In this paper, we present a new approach for parallel simulation of very large scale integration (VLSI) circuits on a transistor level. To achieve good parallel simulation performance on workstation clusters, low communication and coarse grain parallelization is crucial. Two main tasks have to be performed to obtain this target. First, the electronic circuit must be split into subcircuits. To do this, we present an efficient partitioning technique, which yields well-balanced partitions with few interconnects. Second, for minimizing communication between the partitions, sophisticated parallelization methods have to be applied. Therefore, we present our improved domain decomposition technique for parallel analog simulation. The excellent performance of our approach is demonstrated on several industrial VLSI designs. For the first time, good speedup results for parallel analog simulation of large industrial designs are presented.