Large Gate Periphery Research Articles

A Scalable Knowledge-Based Neural Network Model for GaN HEMTs With Accurate Trapping and Self-Heating Effects Characterization

In this article, a scalable knowledge-based neural network (KBNN) large-signal model of gallium nitride (GaN) high-electron-mobility transistors (HEMTs) with accurate trapping and self-heating effects characterization is developed. An improved empirical drain current model is proposed and added to the neural network as prior knowledge, thereby establishing the drain current model, including self-heating effect. A new empirical equation is proposed to model the buffer-related trapping effect more accurately. Taking Angelov capacitance models as prior knowledge, the KBNN capacitance models are completed. Moreover, the scaling characteristics of the proposed KBNN model are studied. The developed model has been fully verified by different sizes of GaN HEMTs. Good agreement between the model simulation results and the measurement data, including current–voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I$</tex-math> </inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V$</tex-math> </inline-formula> ), <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$S$</tex-math> </inline-formula> -parameters, power characteristics, and load-pull data, confirms the effectiveness of the proposed model. The proposed scalable KBNN model is fast and accurate and would be useful for accurate large-signal modeling of large gate periphery GaN HEMTs for high-power radio frequency (RF) applications.

Thermal Analysis of Flip-Chip Bonding Designs for GaN Power HEMTs with an On-Chip Heat-Spreading Layer

In this work, we demonstrated the thermal analysis of different flip-chip bonding designs for high power GaN HEMT developed for power electronics applications, such as power converters or photonic driver applications, with large gate periphery and chip size, as well as an Au metal heat-spreading layer deposited on top of a planarized dielectric/passivation layer above the active region. The Au bump patterns can be designed with high flexibility to provide more efficient heat dissipation from the large GaN HEMT chips to an AlN package substrate heat sink with no constraint in the alignment between the HEMT cells and the thermal conduction bumps. Steady-state thermal simulations were conducted to study the channel temperatures of GaN HEMTs with various Au bump patterns at different levels of current and voltage loadings, and the results were compared with the conventional face-up GaN die bonding on an AlN package substrate. The simulations were started from a single finger isolated HEMT cell and then extended to multiple fingers HEMT cells (total gate width > 40 mm) to investigate the "thermal cross-talk" effect from neighboring devices. Thermal analysis of the GaN HEMT under pulse operation was also performed to better reflect the actual conditions in power conversion or pulsed laser driver applications. Our analysis provides a combinational assessment of power GaN HEMT dies under a working condition (e.g., 1MHz, 25% duty cycle) with different flip chip packaging schemes. The analysis indicated that the channel temperature rise (∆T) of a HEMT cell in operation can be reduced by 44~46% by changing from face-up die bonding to a flip-chip bonding scheme with an optimized bump pattern design.

(Invited) Gallium Oxide Process Development and Integration for Future RF and Power Switching Applications

Beta-phase Gallium Oxide (BGO) is emerging as a high-performance, low-cost electronic device technology for future switching applications. BGO possesses unprecedented critical electric field strength that dominates switch loss figures of merit along with shallow donor energy and large-area native substrates manufactured from the melt. Clear commercial applications exist in vertical Schottky barrier diodes (SBD) offering performance near or surpassing SiC at much lower cost. This commercial pull will mature various BGO transistor applications such as fast-switch power converters made small enough for chip-level process integration.This abstract reviews BGO transistor development progress made by the Air Force Research Laboratory (AFRL) and the community at-large. AFRL has shown record-high transistor critical field strength, low dynamic switch losses surpassing the limit of Si, and early RF small and large signal power performance. Most recently, AFRL has made progress on vertical transistor topologies, self-aligned gate lateral transistors and dielectric optimization. Recent advances for these topics will be discussed and have culminated with large gate periphery BGO power switches and an early demonstration of the first ultra-wide bandgap integrated circuit. The integrated circuit monolithically combines a high-κ capacitor, SBD and power transistor all fabricated on a BGO common substrate.

A comparative study on the accuracy of small-signal equivalent circuit modeling for large gate periphery GaN HEMT with different source to drain length and gate width

In this paper, extrinsic and intrinsic parameters were extracted from the experimental S-parameters using 16- and 22-element small signal equivalent circuit model for large gate periphery GaN HEMT with different source to drain length and gate width over 500 MHz to 26 GHz range. The extraction using 22-element model shows good consistency to measured S-parameters and the maximum gain, stability factor, delta factor and K-factor with less percentage error than 16-element model. As the source to drain length is increasing, the accuracy of parameter extraction is enhanced for 22-element model. Specially for stability factor and K-factor the percentage error was reduced drastically (10.42%–4.74% and 8.13%–0.83% respectively). For increased number of fingers, the 22-element model shows more accuracy. Also, TCAD (Technology Computer-Aided Design) device simulations were done and transfer characteristic were calibrated with measured data. The simulated s-parameters were then calibrated with the experimental extrinsic parameters.

Vertical GaN MISFET for chip‐on‐chip high speed laser driving applications

In this work, the authors developed vertical gallium nitride metal-insulator-semiconductor field-effect transistors (GaN MISFETs) for direct chip-on-chip assembly with gallium arsenide-based broad area distributed Bragg reflector diode laser. The intention of this work had been to provide a high-speed driver solution having extremely small parasitic inductive loops. It is shown that devices manufactured on ammonothermal substrates have large conduction current density above 1.7 kA/cm2, specific on-state resistance as low as 2.1 mΩ·cm2 and on-state sheet resistance of 18.6 Ω·mm. It is further shown that scaling these devices to large gate periphery chips is possible. Finally, a low inductance vertical GaN MISFET on laser diode integration assembly is realised on an AlN ceramic board using a transistor chip with 142 mm gate width and 305 mΩ on-state resistance. The arrangement enables 3.6 ns laser pulses at an emission wavelength at 904 nm and a peak optical power of 4 W.

The Effect of Defects with Deep Levels on the C–V Characteristics of High-Power AlGaN/GaN/SiC HEMTs

This study deals with the capacity–voltage (С–V) characteristics of the gate–drain regions of crystals of high-power microwave HEMT transistors with a large gate periphery of the S and Х bands and a source–drain breakdown voltage VDS ranging from 30 to 150 V, as well as test Schottky diodes formed in a single technological cycle together with HEMTs. Capacitance deep-level transient spectroscopy (DLTS) was used to investigate the structural defects creating deep levels. During the investigations, it was shown that the С–V curves of HEMT crystals always had two areas of change in capacitance with differing slope angles, while there were no such knees in the curves for the test Schottky barriers (SBs). The DLTS technique revealed that НЕМТs and test SBs contained electron-like and hole-like traps, occurring, most probably, in the buffer layer, and also a hole-type peak behaving anomalously. The knee in the С–V curves of НЕМТs is due to the strong electric fields arising at the edge of the gate of the transistor structures.

Systematic design of hybrid high power microwave amplifiers using large gate periphery GaN HEMTs

In this paper, a design methodology for realization of hybrid microwave power amplifiers (PAs) using discrete GaN HEMTs is systematically explained. High power solid-state amplifiers usually suffer from self-heating, high frequency instability, unbalanced feeding effects and suchlike that should be carefully taken into account in a reliable and robust design. Though most of these issues are discussed in some of the previously published literatures, a single self-contained document that systematically describes the hybrid microwave PA design is limited. In this work, a comprehensive design methodology for implementation of high frequency PA is presented while the important challenges of high power amplifier design are discussed in more detail and several useful practical hints are given. Especially, we focus on hybrid PAs that are realized using large gate periphery GaN HEMTs. As a real example, a PA is fabricated using a 0.25 μm GaN on SiC HEMT transistor with a gate width of 12.5 mm. The fabricated PA achieves a 12 dB small-signal gain, 30 W output power, and 52% PAE across the frequency range of 9–9.8 GHz. The thermal analyses of the power transistor are performed using a 3D model, which is developed in ANSYS software and calibrated by measured data. The model can be used to calculate the transistor channel temperature and consequently predict the device lifetime.

GaN‐on‐Si wafers for HEMTs with high power‐driving capability

AbstractBy means of our patented strain engineering technology, we achieved high crystal quality and near zero wafer bow on our 150 mm GaN‐on‐Si wafers. To show the feasibility of our wafers for HEMTs with large gate periphery, we investigated the buffer breakdown(VBR) yield on device test structures with different periphery. To reduce the processing complexity, we used comb‐shaped structures with only source and drain contacts and N+ implant isolation in between the contacts. The VBR was defined at buffer leakage of 1 µA/mm. For a typical source‐drain distance of 14 µm, the VBR yield specification is 600 V. Then we demonstrated over 80% VBR yield for 100 mm device test structures on our 150 mm GaN‐on‐Si wafers. This high yield for large periphery test structures shows that our 150 mm GaN‐on‐Si wafers are very suitable for fabricating large HEMT devices. (© 2014 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

Modelling and simulation of low-frequency broadband LNA using InGaAs/InAlAs structures: A new approach

The ultra-low leakage properties of a novel InGaAs/InAlAs/InP structure have been used to fabricate large gate periphery pHEMTs (up to 1200 μm 2) required for wide band low-noise amplifiers (LNA). The devices were characterized and both linear and non-linear models were extracted. LNAs were then designed and compared favourably with the best results reported to date between 0.3 and 2 GHz, still using a 1 μm gate length optical lithography.

Characterization and modeling of novel large gate periphery InGaAs/ InAlAs pHEMT for ultra low noise radio astronomy applications

Characterization and modeling of novel large gate periphery InGaAs/ InAlAs pHEMT for ultra low noise radio astronomy applications

Coupled electrothermal, electromagnetic, and physical modeling of microwave power FETs

This paper presents a coupled electrothermal, electromagnetic, and physical model for microwave power field-effect transistors (FETs). The resulting model is used to investigate large gate periphery pseudomorphic high electron-mobility transistor devices. The contribution to the output power of each cell of the transistor is simulated, as well as their contribution to the heating of the device. This approach allows the investigation of the interaction between the thermal behavior, the dc bias, and the microwave circuit operating conditions. This paper reveals for the first time a more complex interaction between the thermal and microwave behavior of large-power FETs

Power performance and scalability of AlGaN/GaN power MODFETs

The scalability of power performance of AlGaN/GaN MODFETs with large gate periphery, as necessary for microwave power devices, is addressed in this paper. High-frequency large-signal characteristics of AlGaN/GaN MODFETs measured at 8 GHz are reported for devices with gatewidths from 200 /spl mu/m to 1 mm. 1-dB gain compression occurred at input power levels varying from -1 to +10 dBm as the gatewidth increased, while gain remained almost constant at -17 dB. Output power density was /spl sim/1 W/mm for all devices and maximum output power (29.9 dBm) occurred in devices with 1-mm gates, while power-added efficiency remained almost constant at /spl sim/30%. The large-signal characteristics were compared with those obtained by dc and small-signal S-parameters measurements. The results illustrate a notable scalability of AlGaN/GaN MODFET power characteristics and demonstrate their excellent potential for power applications.

Determination of energy levels of surface states in GaAs metal–semiconductor field-effect transistor using deep-level transient spectroscopy

The energy levels of surface states at the surface of GaAs were determined through capacitance deep-level transient spectroscopy of GaAs metal–semiconductor field-effect transistor with large gate periphery. Two types of hole-like traps are observed in the spectra. These originate from the surface states at the ungated regions between gate and source/drain electrodes. The activation energies of both surface states are determined to be 0.65±0.07 and 0.88±0.04 eV, which agree well with the energy levels of AsGa+ and AsGa++ within band gap of GaAs, responsible for the Fermi level pinning at the surface.

Device characteristics of scaled GaN/AlGaN MODFETs

GaN/AlGaN MODFETs with gate-widths varying from 0.2 to 1 mm have been successfully fabricated, and the device characteristics have been systematically investigated. The epitaxial layers were grown directly on sapphire substrates by RF-assisted MBE. Thick-airbridge technology was employed in the fabrication of large gate periphery devices. Very stable and reproducible device characteristics have been obtained for devices with a total gate width of up to 1 mm. These device results demonstrated the excellent potential of GaN-based FETs as power cells for practical microwave applications.