Large-diameter Silicon Wafers Research Articles

(Invited) Integration of InP Heterojunction Bipolar Transistors on Silicon Substrates for 6G Networks

The power amplifier (PA) in an RF front-end module operating above 100 GHz required for 6G wireless networks is the most power-hungry device circuit component. In that respect, InP-based heterojunction bipolar transistors (HBT) clearly outperform other PA technologies, but being processed on small size wafers, they lack a cost-effective fabrication for mass production. This paper presents a comprehensive comparison of various integration approaches for InP-based HBTs. A key aspect in achieving high yield device fabrication is the use of large-diameter silicon wafers. This study discusses the advantages and disadvantages of different InP-based HBT integration concepts on Si, emphasizing important factors for upscaling InP technologies. Furthermore, this work introduces nano-ridge engineering (NRE), a novel monolithic III-V integration approach currently being explored at imec, which holds the potential for cost-effective and complementary metal oxide semiconductor (CMOS)-compatible production.

Profile control processes based on contact types in silicon wafer DSP manufacturing management

To reduce the manufacturing cost of integrated circuits, the size of the silicon wafer has become larger, with the diameter increasing from 200 to 450 mm. The large diameter silicon wafer poses challenges to the manufacturing process, as its surface profile is more difficult to control and the planarization process is harder to optimize in mass production. Based on different types of contact, gap adjustment and convex pad dressing methods were proposed in this paper to control the pressure distribution on the wafer, which further influenced the wafer profile. Pressure distributions with different gap values and different pad profiles were explained with contact mechanics and verified by simulations. The simulation results show that a negative gap value and a convex pad profile contribute to the improvement of the pressure uniformity on the wafer. Both methods were then applied in the double-sided planarization (DSP) process of 300 mm silicon wafers. The results from the test run of the DSP process show that wafer flatness is improved with a negative gap value. This indicates that gap adjustment is an effective approach for wafer profile control. In the subsequent mass production of the DSP process, silicon wafers with a global flatness of 120 nm and a site flatness of 21.7 nm were obtained.

Kinematic analysis of double-sided polishing of silicon wafers for improving surface flatness

Silicon wafer geometry is stringently controlled at present in the semiconductor industry. In particular, surface flatness must comply with strict standards because it can affect the success of various downstream manufacturing processes. A double-sided polishing (DSP) process serves as the standard finishing process in the industrial manufacture of large diameter silicon wafers. However, nonuniformities in the removal distribution on a wafer in DSP processes cause deterioration of surface flatness of the wafer. In this study, we derive the relation between DSP conditions and the uniformity of the removal distribution and propose better DSP conditions via kinematic modeling of a DSP process.

Influence of ingot rocking on the surface quality of multi-wire sawing monocrystalline silicon wafers

This paper aims on slicing of monocrystalline silicon wafers using a newly developed diamond multi-wire reciprocating saw under ingot rocking process. A contact wire length model based on ingot rocking was established. The influence of motion parameters of ingot rocking on the surface quality of multi-wire sawn monocrystalline silicon wafers had been experimentally studied. The slicing surface morphology, surface roughness, and surface hardened layer were investigated by using scanning electron microscope, laser scanning microscopy, and microhardness tester. Results show that compared with the multi-wire cutting mode with an ingot rocking amplitude of 0°, ingot rocking (θm ≠ 0) can reduce the contact wire length of sawing by almost half at any time, and realize discontinuous and segmented sawing of large-diameter silicon wafers. By reducing the contact wire length, the cutting mode under ingot rocking can achieve better surface morphologies, and reduce roughness, thickness of the hardened layer and microhardness of the surface in silicon wafer cutting. Compared with the mode of multi-wire reciprocating sawing with an ingot rocking amplitude of 0°, an ingot rocking amplitude of 5°can reduce roughness, thickness of the hardened layer, and microhardness of the surface in silicon wafer cutting about 30.1%, 20.1%, and 11.3%. Though the ingot rocking amplitude did not significantly influence the contact wire length during the cutting process, the ingot rocking motion significantly influences the ingot feed speed, an ingot rocking amplitude of 5°instead of 3° or 7° is suggested for the best surface quality.

Excellent Rectifying Properties of the n-3C-SiC/p-Si Heterojunction Subjected to High Temperature Annealing for Electronics, MEMS, and LED Applications

This work examines the stability of epitaxial 3C-SiC/Si heterojunctions subjected to heat treatments between 1000 °C and 1300 °C. Because of the potential for silicon carbide in high temperature and harsh environment applications, and the economic advantages of growing the 3C-SiC polytype on large diameter silicon wafers, its stability after high temperature processing is an important consideration. Yet recently, this has been thrown into question by claims that the heterojunction suffers catastrophic degradation at temperatures above 1000 °C. Here we present results showing that the heterojunction maintains excellent diode characteristics following heat treatment up to 1100 °C and while some changes were observed between 1100 °C and 1300 °C, diodes maintained their rectifying characteristics, enabling compatibility with a large range of device fabrication. The parameters of as-grown diodes were J0 = 1 × 10−11 A/mm2, n = 1.02, and +/−2V rectification ratio of 9 × 106. Capacitance and thermal current-voltage analysis was used to characterize the excess current leakage mechanism. The change in diode characteristics depends on diode area, with larger areas (1 mm2) having reduced rectification ratio while smaller areas (0.04 mm2) maintained excellent characteristics of J0 = 2 × 10−10 A/mm2, n = 1.28, and +/−2V ratio of 3 × 106. This points to localized defect regions degrading after heat treatment rather than a fundamental issue of the heterojunction.

Development of Piezoelectric Three-Dimensional Dynamometer for Φ300mm Wafer Grinder

Due to the requirements of on-line detection of grinding force in the grinding process, this paper utilizes the structural characteristics of ultra-precision grinder with double-spindle and single-workstation, and then presents a grinding dynamometer based on piezoelectric effect of quartz crystals. Besides, the grinder dynamometer can measure grinding force in three directions, and the static properties of dynamometer are experimentally tested in a special experiment table. Moreover, the on-line static calibration and the actual grinding experiment of dynamometer installed in the silicon wafer grinder are performed. The results indicate that the grinding dynamometer has satisfactory static properties, that is, the linearity and repeatability are less than 1%, and the cross-talks are also less than 5%. As a result, each indicator has full reached the operating requirements in using of large diameter silicon wafer grinding force measuring.

Features of defect formation under the thermal treatment of dislocation-free single-crystal large-diameter silicon wafers with the specified distribution of oxygen-containing gettering centers in the bulk

Possibilities of obtaining a defect-free layer in wafers of dislocation-free single-crystal silicon subjected to rapid thermal annealing (RTA) are analyzed. The application of RTA is based on the possibility of effectively affecting the distribution profile of the density of oxygen precipitates over the wafer thickness by means of controlling the distribution profiles of the vacancies and interstitial atoms. However, the solution of this important task encounters the problem of the appearance of large local stresses in the vicinity of the fastening supports of a large-diameter silicon wafer and its bending in the course of RTA, which are caused by its own weight. Using mathematical modeling of the three-dimensional stress-strain state and defect formation in large-diameter silicon wafers in the course of RTA, various methods of fastening the wafers are considered and the possibilities of lowering the stress-strain state of the silicon wafer are determined. A mathematical model taking into account the diffusion-recombination processes of vacancies and interstitial silicon atoms, as well as the formation of vacancy clusters is proposed to describe the defect formation in the course of RTA. Based on this model, temperature-temporal parameters of RTA, which correspond to the required (depleted near the surface) concentration profile of the vacancies and the density and size of the vacancy clusters over the wafer thickness, are determined (heating time, holding time at the highest temperature, the cooling rate of the wafer). The results of the calculations are verified for test samples using optical microscopy and transmission electron microscopy (OM and TEM).

Formation speed of atomically flat surface on Si (1 0 0) in ultra-pure argon

The flattening speed of the low temperature atomically flattening technology is evaluated in order to apply atomically flat surface of (1 0 0) orientation on large-diameter silicon wafers to the LSI manufacturing. The atomically flatness of the whole surface of wafers with the diameter of 200 mm can be obtained after annealing at 800 °C or above. The process time required to obtain the atomically flatness for the whole wafer surface can be shortened by increasing the annealing temperature as well as by increasing the gas flow rate. With the off angle of 0.50° or below, it was found that only mono-atomic steps appear on the surfaces and the flattening speed is independent of the off angle. These indicate that the process speed is independent of the migration speed of Si atoms on the surface, but depends on the gas replacement efficiency near the Si surface in this technique.

Development of a high-frequency pulse laser irradiation system for repairing silicon wafers damaged by abrasive machining processes

A four-axis numerically controlled precision stage equipped with a high-frequency nanosecond pulsed Nd:YAG laser system was developed for processing grinding-damaged silicon wafers. The resulting specimens were characterised using a white-light interferometer, a micro-Raman spectroscope and a transmission electron microscope. The results indicate that around the laser beam centre where the laser energy density is sufficiently high, the grinding-induced amorphous silicon was completely transformed into the single-crystal structure. The optimum conditions for one- and two-dimensional overlapping irradiation were experimentally obtained for processing large-diameter silicon wafers. It was found that the energy density level required for completely removing the dislocations is higher than that for recrystallising the amorphous silicon. After laser irradiation, the surface unevenness has been remarkably smoothed.

Processing Grinding-Damaged Silicon Wafers by High-Frequency Nano-Second Laser Irradiation

Ultraprecision diamond-ground silicon wafers were irradiated by a high-frequency nanosecond pulsed Nd:YAG laser equipped on a four-axis numerically controlled stage. The resulting specimens were characterized using a white-light interferometer, a micro-Raman spectroscope and a transmission electron microscope. The results indicate that around the laser beam center where the laser energy density is sufficiently high, the grinding-induced amorphous silicon was completely transformed into the single-crystal structure. The optimum conditions for one- and two-dimensional overlapping irradiation were experimentally obtained for processing large-diameter silicon wafers. It was found that the energy density level required for completely removing the dislocations is higher than that for recrystallizing the amorphous silicon. After laser irradiation, the surface unevenness has been remarkably flattened.

Atomically Flat Silicon Surface and Silicon/Insulator Interface Formation Technologies for (100) Surface Orientation Large-Diameter Wafers Introducing High Performance and Low-Noise Metal–Insulator–Silicon FETs

Technology to atomically flatten the silicon surface on (100) orientation large-diameter wafer and the formation technology of an atomically flat insulator film/silicon interface are developed in this paper. Atomically flat silicon surfaces composed of atomic terraces and steps are obtained on (100) orientation 200-mm-diameter wafers by annealing in pure argon ambience at 1200 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">deg</sup> C for 30 min. Atomically flat surfaces with various terrace widths and step structures are observed by atomic force microscopy. It is found that the atomic terrace width changes widely with an off angle of the wafer surface from the (100) lattice plane. It is also found that the direction of the off angle significantly affects the atomically flat surface morphology, i.e., when the directions of the off angles are parallel to the <110> directions, the step structure is composed of alternating pairs of straight and triangular steps. When the directions of the off angles are parallel to the <100> directions, the step structure is composed of only straight steps. By precise control of the off angle and the direction toward the <100> directions for a 200-mm-diameter silicon wafer, we have succeeded in fabricating an atomically flat surface with straight atomic steps and a very uniform terrace width of 140-150 nm on the entire surface of a large-diameter silicon wafer. Furthermore, it is found that only radical-reaction-based insulator film formation technology, such as oxidation utilizing oxygen radicals carried out at a low temperature (400 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">deg</sup> C ), preserves the atomic flatness of the insulator film/silicon interface. Finally, when MOSFETs are fabricated with an atomically flat interface, they exhibit near ideal subthreshold swing factors, with much smaller fluctuation, extremely lower 1/ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> noise, and higher MOS dielectric breakdown field intensity compared with MOSFETs fabricated with conventional technologies.

S1302-2-6 レーザ照射による大口径単結晶シリコンウエハの加工欠陥修復に関する研究(超精密加工(2))

S1302-2-6 レーザ照射による大口径単結晶シリコンウエハの加工欠陥修復に関する研究(超精密加工(2))

Achievement of High Flatness of Large Diameter Silicon Wafer in Double-Sided Polishing (Optimization of Polishing Conditions Based on Kinematical Analysis)

Silicon (Si) wafers are the most commonly used substrates for the production of semiconductor devices. The design rule is miniaturization, and the chip size is increasing to improve the degree of the device integration. As the substrate, Si wafer is then required to be manufactured with higher flatness and larger diameter in order to meet the above demand. The double-sided polishing process is widely adopted as the finishing stage of the wafer manufacturing, because wafers with good surface quality and flatness can be obtained economically. However, the polishing technology has a serious problem : it is very difficult to set the appropriate conditions for stably polishing the Si wafer and wearing pad to high flatness in manufacturing. In this study, the optimization of double-sided polishing conditions was proposed and developed for overcoming the problem. As a basis, the model of the distribution of material removal on the wafer and the distribution of wear on the pad was developed based on kinematical analysis. The amounts of removal and wear are considered to be proportional to the sliding distance between wafer and pads. The optimization of the polishing conditions was performed utilizing a quasi-Newton method. As a result, the polishing conditions are clarified by minimizing the deviation of material removal distribution on the wafer and wear distribution on the pads, that is, achieving high flat wafer and pads.

Effects of support method and mechanical property of 300 mm silicon wafer on sori measurement

This paper describes the effects of support methods and mechanical properties of 300 mm silicon wafer on sori measurement. A new supporting method, named three-point-support method, used in the sori measurement of a large diameter silicon wafer was proposed in this study to obtain a more stable measuring process. The wafer was supported horizontally by three steel balls on the vertexes of a regular triangle at the wafer edge. The measuring repeatability and anti-disturbance ability were compared between the proposed method and the conventional one-point-support method, in which the wafer is supported with a small-area chuck at the wafer center. The effects of friction between the supports and wafer surface for the three-point-support were also estimated. Finally, the influences of different mechanical characteristics at the front and back surfaces and the crystal orientation on sori measurement were investigated.

Simulation of the stresses produced in large-diameter silicon wafers during thermal annealing

The three-dimensional problem of stress and strain fields in dislocation-free silicon wafers 200 and 300 mm in diameter placed horizontally on three symmetrical supports and subjected to is gravitational forces and thermal stresses formulated and solved in the isotropic approximation. Under the action of gravitational forces, a wafer is shown to have the lowest total stress when the supports are positioned at a distance of 0.6–0.7R from the center of the wafer. The shear-stress fields are calculated for all possible slip systems. The elastic-stress field in a 300-mm wafer is found to be induced mainly by gravitational forces even at a radial temperature gradient of 10 K. At this temperature gradient, the contribution from thermal stresses in a 200-mm wafer is comparable to the contribution from gravitational forces. At radial temperature gradients lower than 5 K, the contribution from thermal stresses can also be neglected for a 200-mm wafer. The maximum shear stresses calculated indicate that one should not neglect possible dislocation generation in the zone of contact between a wafer and the supports during high-temperature annealing of 200-mm and, especially, 300-mm wafers.

Diffuse x-ray scattering study of the formation of microdefects in heat-treated dislocation-free large-diameter silicon wafers

Diffuse x-ray scattering (DXS) is used to study the formation of microdefects (MDs) in heat-treated dislocation-free large-diameter silicon wafers with vacancies. The DXS method is shown to be efficient for investigating MDs in silicon single crystals. Specific defects, such as impurity clouds, are found to form in the silicon wafers during low-temperature annealing at 450°C. These defects are oxygen-rich regions in the solid solution with diffuse coherent interfaces. In the following stages of decomposition of the supersaturated solid solution, oxide precipitates form inside these regions and the impurity clouds disappear. As a result of the decomposition of the supersaturated solid solution of oxygen, interstitial MDs form in the silicon wafers during multistep heat treatment. These MDs lie in the {110} planes and have nonspherical displacement fields. The volume density and size of MDs forming in the silicon wafers at various stages of the decomposition are determined.

X-ray characterization of crystal perfection and surface contamination in large-diameter silicon wafers

This paper reviews recent development of X-ray techniques, which cover laboratory experiments and synchrotron radiation (SR) applications, to detect crystal imperfections and surface contamination in large-diameter Czochralski-grown silicon (CZ-Si) wafers. While process-induced defects can be easily detected by a large-sized Lang camera, it is difficult to observe grown-in microdefects and slight impurity-inhomogeneity even when the double-crystal method is applied. SR plane-wave X-ray topography has overcome this difficulty, except for observing void defects, with the help of its high strain sensitivity although it cannot be directly applied to large Si wafers because of their warpage. Recently, SR X-ray topography using a 300-mm-wide monochromatic beam has been employed for measuring the warpage of 200- and 300-mm wafers as well as inspecting surface damage caused by various steps of wafer-manufacturing. Although energy-dispersive total-reflection X-ray fluorescence analysis using a rotating-anode X-ray generator is now widely used for detecting traces of metallic impurities on the surface of 300-mm Si wafers, the requirement of a large scale integrated circuit miniaturization has promoted the combination of a vapor-phase decomposition technique and the TXRF for lowering the lower-limit of detection (LLD). SR-TXRF using an ED solid-state detector is effective in nondestructive and low LLD features, while newly developed wavelength-dispersive (WD) SR-TXRF in good energy resolution. The combined use of the laboratory and SR experiments leads to precise information about crystal perfection and surface contamination in large-diameter Si wafers.

Thermal Behavior of Large-Diameter Silicon Wafers during High-Temperature Rapid Thermal Processing in Single Wafer Furnace

Thermal behavior of 200-mm- and 300-mm-diameter Si (100) wafers during high-temperature rapid thermal processing (RTP) in a single wafer furnace (SWF) is investigated as a function of temperature, pressure, process time, wafer handling method and speed. Significant elastic wafer shape deformation was observed during wafer temperature ramp-up. Slip generation was frequently observed in wafers processed above 1050°C. Size, shape and spatial distribution of crystal defects generated during RTP were characterized using an optical microscope and X-ray topography. The wafer handling method and speed are found to be very important in reducing defect generation during RTP at the given process conditions. Highly reproducible, slip-free RTP results were achieved in 200-mm- and 300-mm-diameter Si (100) wafers processed at 1100°C by optimizing the wafer handling method and speed.

Synchrotron-radiation X-ray topography of surface strain in large-diameter silicon wafers.

Using a 300 mm-wide monochromatic X-ray beam obtained at beamline BL20B2 of SPring-8, the difference in surface-strain distribution caused by various steps of silicon-wafer manufacturing, i.e. slicing, lapping, etching, grinding and polishing, was studied. The asymmetric 511 reflection of 21.45 keV X-rays, incident at a glancing angle of 0.26 degrees, was used to obtain topographs over the whole surface of a 200 mm-diameter (100) CZ silicon wafer. Differences in crystallinity and in warp between the surfaces at different steps of the manufacturing process (firstly after the lapping following the slicing, and then after successive etching, grinding and polishing) were clearly observed. The former gave a topographic image over the whole area with a one-shot exposure because of their wide rocking curves (50-70 arcsec FWHM), which indicate poor crystallinity. The latter, on the other hand, showed sharper curves (4-5 arcsec FWHM), which indicate good crystallinity in local areas, and the existence of warp, and therefore required step scanning of omega-rotation to cover the whole surface in topography measurements. The effect of each step in the process is also discussed.

Comparative Study on Surfaces of Single-Crystalline Substrates. From Dielectric Substance to Semiconductor and Metal. Machining and Processing Technologies and Quality of Silicon Wafer Surfaces.

The current state of the technologies of machining and processing of silicon wafers is described. The 8 inches diameter wafer process is just shifting to the process for 12 inches wafers. Actually, in wafer plants it is necessary to reconsider the wafer making methods which have been used so far. For instance, the method of wafer slicing is changing to multi-wire lapping from grinding with inner type thin diamond wheels, since the preparation of thinner and wider wheel metal plates becomes impossible for prospective large diameter silicon wafers. In wafer surface finishing, the present lapping and polishing methods will be replaced with a kind of grinding method using abrasive wheels as in glass lens manufacturing. However it might not become realistic soon, and, for the time being, the current conditions of lapping and chem-mechanical polishing will be utilized. The stock removing mechanism and the damaged layer in lapping or polishing are given an account.