Large-diameter Silicon Wafers Research Articles

Modeling Stresses of Contacts in Wire Saw Slicing of Polycrystalline and Crystalline Ingots: Application to Silicon Wafer Production

Wire saw slicing is a cost effective technology with high surface quality for slicing large diameter silicon wafers. Though wire saws have been deployed to cut polycrystalline and single crystal silicon ingot since the early 1990s, very little is known about the fundamental cutting process. We investigate this manufacturing process and propose a contact stress model of wire saw slicing that illustrates the interactions among the wire, ingot, and abrasives (e.g., SiC) carried by the slurry. Stresses created by wire saw slicing silicon wafers are analyzed in this paper. During the cutting process, the wire moves at high speed (5–15 m/s) with respect to the silicon ingot. The abrasives in the slurry are lose third-body particles caught between the wire and ingot at the contact surface. The forces applied by the wire carry the abrasive particles and cause them to roll on the surface and at the same time to be constrained to indent the surface. Such rolling-indenting interactions result in the formation of isolated chips and surface cracks. The cracks and discontinuity on the surface also cause high stress concentration. As a result, the material is cut and removed. The stress fields of a single circular cone of the abrasive particle indenting on silicon crystal with normal and tangential forces can be calculated and analyzed from the modeling equations and boundary conditions. The stresses are expressed with dimensionless stress measures, as functions of normalized geometric parameters. The results show that the maximum normal stress occurs at the indentation point, while the maximum shear stress (σzx) occurs below the surface of contact, as expected. Such subsurface shear facilitates the peeling effects of the silicon cracks. Both the normal and tangential forces applied at the contacts are incorporated in the model. The model is very effective in explaining and predicting the behaviors and distributions of stresses during the cutting process, and can be used to determine the optimal geometry of the abrasive particles in the rolling-indenting process.

Haze Generation on Silicon Surface Heated in Hydrogen Ambient at Atmospheric Pressure

The change in surface roughness of a silicon wafer with temperature is studied using a dry system composed of quartz parts, a small silicon carbide part, a lamp‐heating module, and hydrogen ambient at atmospheric pressure. A large diameter silicon wafer having a large temperature gradient is heated at 850 to 1100°C. Haze appears on the silicon surface and shifts from the higher temperature region to the lower temperature region of the wafer with increasing wafer temperature and finally disappears at temperatures higher than 1000°C. The temperature range in which the haze is generated due to surface pit formation is shown to be 900 to 1000°C. The influence of moisture in the gas phase on haze generation is considered to be very small. The surface pit formation is essentially due to the difference between the etch rates of silicon and silicon dioxide by hydrogen gas.

Computer Simulation of Stress Induced Dislocation Multiplication in Large-Diameter Silicon Wafer in High-Temperature Device Processing

The occurence of slip bands due to stresses in large-diameter Czochralski-grown silicon (Si) wafers was studied with computer simulation to maintain them dislocation-free in ultra-large-scale-integrated-circuits (ULSIs) manufacturing. Two types of stresses induced in the circular wafers are investigated; thermal stress originated either in radial temperature variation or in gravitational stress due to the bending moment caused by the wafer's weight itself. Since the advent of 200-mm-dia wafer era for devices, slip bands generated by the gravitational stress were discovered, extending from the point jig as elongated slippages along the directions, in addition to those due to thermal stresses. On a simplified model wherein the point jig was assumed to be a solid line, resolved shear stresses due to the gravitational stress were calculated for the 300-mm-dia wafer, which is considered to be the wafer size of the next generation. On the basis of the previously proposed thermoelastic model, critical stress curves to multiply slip dislocations were obtained as a function of microdefect density, which acts as nucleation sites for dislocation multiplication, thereby softening Si wafers under mechanical stress. By comparing both the gravitational stress and the critical stresses, conditions to suppress slip bands due to the gravitational stress in device processings are described as predictable in wafers larger than 300 mm in diameter and moreover those to suppress slip dislocations due to thermal stress were also predicted. The physical meaning of the critical stress curve is discussed by comparing with the upper yield stress obtained in conventional tensile tests.

Stress and Warpage Studies of Silicon Based Plain and Patterned Films During Rapid Thermal Processing (RTP)

ABSTRACTSingle wafer rapid thermal processing (RTP) is emerging as a key player in the processing of advanced sub-half micron memory devices. The high temperature processing of large diameter silicon wafers can create sufficient thermal stress for generation of dislocation, slip, and gross mechanical instability of the wafer. The aforementioned factors may lead to loss of device yield, dielectric defects, and reduced photolithographic yield due to degradation of virtual wafer flatness. Moreover, the loss of geometrical planarity of wafer due to warpage can make it impossible to process a wafer or can lead to self-fracture of the wafer.In this paper we present the warpage and stress results of our study on plain and patterned structures that were subjected to RTP at different stages of the CMOS process flow. Experimental results have been gathered with full wafer scanning technology using non-contact capacitive probes to measure more accurate global stress values. The stress and warpage values on the patterned wafers could be measured accurately without any light scattering effects and destructive interference. It is reported that the thermal processing creates significant variations in shape change around the wafer which could be identified using the full wafer data set acquired using this evaluation technique. We have successfully tracked variations in film stress for both plain and patterned structures as a cumulative effect and correlated it with the overall wafer warpage. The effects of incoming wafer warpage, ramp rate in RTP, and high stress nitride films on the overall wafer warpage are also reported.

Assessment of Metallic Trace Contaminants on Silicon Wafer Surfaces

ABSTRACTNeutron activation, atomic absorption, and voltammetric techniques are presented as appropriate analytical tools to monitor trace amounts of metallic impurities on large diameter silicon wafers. Detection limits and results are compared for standard wafers implanted with Fe, Cu, and Ni. DLTS measurements are included for implanted and as-grown doped wafers.

Photovoltaic Technique for Measuring Resistivity Variations of High Resistivity Silicon Slices.

A description of an automated, photovoltaic system for measuring the resistivity variation of high resistivity, large diameter silicon wafers is given. The photovoltaic technique utilizes a scanning light spot to induce a bulk photovoltage and a change in resistance from which is calculated the local variation in resistivity. This nondestructive technique requires no contacts to the useful fabrication area of the wafer, and measured results have good correlation with the results of the four-probe technique. Specific examples of measured resistivity gradients are presented along with a discussion of the theory, measurement conditions and limitations, and description of a calculator-based automated system to perform the measurements.

Lang camera for large scale X-ray transmission topography. (Nondestructive test method for Si wafer quality control)

An X-ray topography camera of the Lang type with a scanning range of about 30 cm is described which is capable of recording in one run topographs of e.g. four 3 in diameter silicon wafers. Camera performance and the use of the setup for quality control of large diameter silicon wafers are illustrated.