Large-area Flexible Electronics Research Articles

Sintering of Copper Nanoparticles using Intense Pulsed Light for screen-printed films on flexible substrate

Abstract Rapid growth in applications involving large area flexible electronics has led to wide adoption of the technique of sintering printed films using intense pulsed light (IPL) due to its pulse mode operation and ability to reach high sintering temperatures without affecting the underlying substrate significantly. We study sintering mechanisms of screen-printed thin films of copper nanoparticles on polyethylene terephthalate (PET) plastic substrate by varying irradiance energy over a wide range to monitor conductivity and associated microstructure changes. We obtain optimized parameters which indicate existence of a sharp threshold irradiance energy to kickstart sintering, and two distinct regimes beyond that. The low temperature regime has a high energy barrier while the high temperature regime has a substantially reduced energy barrier with change of phase due to local melting.

Inkjet-printed p-type tellurene and n-type MoS2 transistors for CMOS electronics

Abstract Two-dimensional semiconductor materials combine exceptional electronic transport properties with mechanical flexibility and hence can be an ideal choice for large-area flexible and wearable electronics. While inkjet printing may be a suitable approach to fabricate high throughput electronic components on polymer substrates, solution-processed 2D semiconductor network transistors suffer from two major hindrances: extremely high inter-flake resistance and the lack of high-performance p-type semiconductors. This study shows that inkjet-printed tellurium nanowires or tellurene nanoflakes can offer high-performance p-type TFTs with current density up to 100 μA/μm and an On-Off ratio >105. In order to circumvent the high inter-flake junction resistance, a narrow-channel, near-vertical device architecture has been used that ensures predominantly intra-flake/ intra-nanowire transport, which resulted in three orders of magnitude increase in the current density compared to conventional devices without compromising on the On-Off ratio. Moreover, we show the whole device operation within ± 2 V, with a threshold voltage close to 0 V. The complete device fabrication is carried out at room temperature, thereby making it compatible with inexpensive polymer substrates. Next, outstanding device performance has also been realized with electrochemically-exfoliated and inkjet-printed n-type MoS2 TFTs, demonstrating a current density of 60 μA/μm and an On-Off ratio of 106. Furthermore, we show tellurene-based p-type depletion-load unipolar inverters and CMOS inverters alongside n-type MoS2 TFTs, demonstrating a signal gain of 12 and 11, respectively. The CMOS inverters are found to operate at a frequency of 1 kHz.

Design and Characterization of High Quality-Factor Inductors for Wireless Systems Compatible With Flexible Large-Area Electronics

Design and Characterization of High Quality-Factor Inductors for Wireless Systems Compatible With Flexible Large-Area Electronics

Reaching High Piezoelectric Performance with Rotating Directional-Field-Aligned PVDF-MoS2 Piezo-Polymer Applicable for Large-Area Flexible Electronics.

Wearable electronics and smart harvesting textile studies require a material system that resists physical stimulation. Such applications require receptive piezo-polymers, and their activation-free preparation that can translate into a continuous large-area film. In this work, it is discussed whether the β-content of piezo-polymer is extended with no use of any activation (i.e. poling), and if the β-content increases, it can be processed over a wide range of surfaces like large-area piezo-film. Such prerequisites within polyvinylidene fluoride-molybdenum disulfide ((PVDF)-MoS2 ) piezo-polymer are thoroughly experimented here to develop a high-performance piezo-film. A MoS2 -mediated PVDF piezo-polymer (termed as P+ -MoS2 ) is introduced, in which no extra β-enhancement activation step is required after spin coating. Experimental results record β ≧ 80% which allows to harvest the voltage and current in the level of ≈17 V and 1 µA, respectively which satisfies 5 V supply voltage requirement of the current microelectronics, and internet of things (IoT). In addition, the capacitors having different capacities are charged using the developed nanogenerator to check its practical applicability. Therefore, the transition process of P-MoS2 to aligned P+ -MoS2 due to passive interlocking (PiL) through rotating directional field is novel and found to be a principal reason for β-enhancement in fabricated devices.

Nano-Scale Ga2O3 Interface Engineering for High-Performance of ZnO-Based Thin-Film Transistors

Thin-film transistor (TFT) is a essential device for future electronics driving the next level of digital transformation. The development of metal-oxide-semiconductor (MOS) TFTs is considered one of the most advantageous devices for next-generation, large-area flexible electronics. This study demonstrates the systematic study of the amorphous gallium oxide (a-Ga2O3) and its application to nanocrystalline ZnO TFTs. The TFT with a-Ga2O3/c-ZnO-stack channel exhibits a field-effect mobility of ∼41 cm2 V-1 s-1 and excellent stability under positive-bias-temperature stress. The a-Ga2O3/c-ZnO-stack TFT on polyimide (PI) substrate exhibits a negligible threshold voltage shift upon 100k bending cycles with a radius of 3 mm and is very stable under environmental test. The smooth morphology with tiny grains of ∼12 nm diameter with fewer grain boundary states improves the charge transport in Ga2O3/ZnO-stack TFT. The existence of amorphous a-Ga2O3 in between very thin ZnO layers helps to enhance the heterointerfaces and reduce the defect density in Ga2O3/ZnO interface. Therefore, integrating a-Ga2O3 in the ZnO channel in stacked TFT can increase mobility and enhance stability for next-generation flexible TFT electronics.

Thin-Film Transistors from Electrochemically Exfoliated In2Se3 Nanosheets.

The wafer-scale fabrication of two-dimensional (2D) semiconductor thin films is the key to the preparation of large-area electronic devices. Although chemical vapor deposition (CVD) solves this problem to a certain extent, complex processes are required to realize the transfer of thin films from the growth substrate to the device substrate, not to mention its harsh reaction conditions. The solution-based synthesis and assembly of 2D semiconductors could realize the large-scale preparation of 2D semiconductor thin films economically. In this work, indium selenide (In2Se3) nanosheets with uniform sizes and thicknesses were prepared by the electrochemical intercalation of quaternary ammonium ions into bulk crystals. Layer-by-layer (LbL) assembly was used to fabricate scalable and uniform In2Se3 thin films by coordinating In2Se3 with poly(diallyldimethylammonium chloride) (PDDA). Field-effect transistors (FETs) made from a single In2Se3 flake and In2Se3 thin films showed mobilities of 12.8 cm2·V−1·s−1 and 0.4 cm2·V−1·s−1, respectively, and on/off ratios of >103. The solution self-assembled In2Se3 thin films enriches the research on wafer-scale 2D semiconductor thin films for electronics and optoelectronics and has broad prospects in high-performance and large-area flexible electronics.

Alignment of Organic Conjugated Molecules for High-Performance Device Applications.

High-performance organic semiconductor materials as the electroactive components of optoelectronic devices have attracted much attention and made them ideal candidates for solution-processable, large-area, and low-cost flexible electronics. Especially, organic field-effect transistors (OFETs) based on conjugated semiconductor materials have experienced stunning progress in device performance. To make these materials economically viable, comprehensive knowledge of charge transport mechanisms is required. The alignment of organic conjugated molecules in the active layer is vital to charge transport properties of devices. The present review highlights the recent progress of processing-structure-transport correlations that allow the precise and uniform alignment of organic conjugated molecules over large areas for multiple electronic applications, including OFETs, organic thermoelectric devices (OTEs), and organic phototransistors (OPTs). Different strategies for regulating crystallinity and macroscopic orientation of conjugated molecules are introduced to correlate the molecular packing, the device performance, and charge transport anisotropy in multiple organic electronic devices.

Experimental and modeling study of controllable laser lift-off via low-fluence multiscanning of polyimide-substrate interface

Fabricating large-area thin-film flexible electronics rely on the peeling process from rigid prefabricated carriers. The well-established laser lift-off (LLO) employs a shaped excimer laser to scan the interfacial polyimide (PI) for peeling. However, using the traditional LLO (high-fluence single scanning), nondestructive peeling of ultra-thin fragile devices remains challenging. Here, an enhanced LLO strategy based on multiple low-fluence irradiations with an excimer laser (m-LLO) is studied to perform noninvasive and controllable peeling. We first construct a model predicting the core parameter of the peeling effect, the amount of gas accumulated at the interface generated by multiple backside irradiations. The specific influence of gas on the peeling effect is obtained through the accurate assessment of the interface bonding state by profile analysis, micro-observations, and strain sensing. We establish a deterministic peeling method by providing the peeling index that can precisely evaluate the interface bonding state under different process parameters, showing advantages over traditional LLO. The characterizations of chemical modifications after peeling further confirmed a different process mechanism of m-LLO. These results would be helpful to develop a non-destructive and controllable LLO process for the mass production of the next generation of flexible electronics.

Layout-to-Bitmap Conversion and Design Rules for Inkjet-Printed Large-Scale Integrated Circuits

Digital inkjet printing (IJP) can greatly reduce the manufacturing cost and waste of flexible large-area electronics by adding micro-fine patterns onto plastic foils. Advanced system design using IJP has been limited by the lack of an electronic design automation (EDA) approach. An EDA approach based on a vector-based layout drawing requires parameterized IJP design rules. This study proposes a layout-to-bitmap (L2B) conversion procedure and line-based design rules that leverage the existing circuit layout EDA tools for advanced IJP designs. The L2B conversion is accomplished by optimizing the parameters of the horizontal and vertical lines by varying the drop spacings and platen temperatures. Next, the line-based layouts are converted to bitmap files which are used as IJP input data for printing multiple metal layers. This study systematically investigated the development of an IJP process employing Ag nanoparticles. The physical characteristics of the proposed process were evaluated based on theories concerning inkjet-printed bead formation. The design rules for fabricating printed thin-film transistor (TFT) circuits were documented. Documentation is the first step in creating an IJP process design kit for advanced electronics design. Using the optimized L2B conversion procedure and the design rules, a 10 × 10 array of printed organic TFTs was fabricated to demonstrate the reliability of the developed process. Additionally, the fabricated printed organic TFTs indicated that the proposed process could be extended to large-scale system designs.

Reduction of leakage current in amorphous Oxide-Semiconductor Top-gated thin film transistors by interface engineering with dipolar Self-Assembled monolayers

Top gate (TG) thin film transistors (TFTs) featuring amorphous metal oxide semiconductors (a-MOS), such as indium-gallium-zinc-oxide (IGZO), bear a great potential for large-area flexible and transparent electronics. The fabrication costs of these devices can be noticeably reduced by introduction of solution processes instead of standard fabrication routes involving vacuum deposition and complicate photolithography. However, solution-processed TG a-MOS TFT often causes considerable gate leakage in comparison with vacuum-processed device. In this context, we present a simple and straightforward approach to reduce the gate leakage of IGZO-based TG TFTs, which predominantly involves solution-based procedures. We engineer the IGZO/insulator interface by dipolar, silane-anchored self-assembled monolayers (SAMs) providing a favorable built-in electric field to reduce the leakage current in TFTs. The parameter correlates well with the direction and value of the molecular dipole moment defined by either electron accepting or electron donating character of the terminal tail group. These SAMs, prepared by spin-coating procedure, were characterized in detail by a combination of several complementary experimental techniques, providing also a useful background information for the device experiments.

Recent trends and role of large area flexible electronics in shape sensing application – a review

PurposeThis paper aims to review the shape sensing techniques using large area flexible electronics (LAFE). Shape perception of humanoid robots using tactile data is mainly focused.Design/methodology/approachResearch papers on different shape sensing methodologies of objects with large area, published in the past 15 years, are reviewed with emphasis on contact-based shape sensors. Fiber optics based shape sensing methodology is discussed for comparison purpose.FindingsLAFE-based shape sensors of humanoid robots incorporating advanced computational data handling techniques such as neural networks and machine learning (ML) algorithms are observed to give results with best resolution in 3D shape reconstruction.Research limitations/implicationsThe literature review is limited to shape sensing application either two- or three-dimensional (3D) LAFE. Optical shape sensing is briefly discussed which is widely used for small area. Optical scanners provide the best 3D shape reconstruction in the noncontact-based shape sensing; here this paper focuses only on contact-based shape sensing.Practical implicationsContact-based shape sensing using polymer nanocomposites is a very economical solution as compared to optical 3D scanners. Although optical 3D scanners can provide a high resolution and fast scan of the 3D shape of the object, they require line of sight and complex image reconstruction algorithms. Using LAFE larger objects can be scanned with ML and basic electronic circuitory, which reduces the price hugely.Social implicationsLAFE can be used as a wearable sensor to monitor critical biological parameters. They can be used to detect shape of large body parts and aid in designing prosthetic devices. Tactile sensing in humanoid robots is accomplished by electronic skin of the robot which is a prime example of human–machine interface at workplace.Originality/valueThis paper reviews a unique feature of LAFE in shape sensing of large area objects. It provides insights from mechanical, electrical, hardware and software perspective in the sensor design. The most suitable approach for large object shape sensing using LAFE is also suggested.

Chemical-free transfer of patterned reduced graphene oxide thin films for large area flexible electronics and nanoelectromechanical systems

In this paper, a wet-dry hybrid technique to transfer patterned reduced graphene oxide (rGO) thin film to arbitrary substrates at predetermined locations without using any chemicals is reported. The transfer process involves water-assisted delamination of rGO, followed by dry transfer to an acceptor substrate using viscoelastic stamp. Patterned reduced graphene oxide films are transferred to silicon dioxide (SiO2/Si) substrate to begin with. Subsequently, the method is deployed to transfer rGO to different polymer substrates such as poly(methyl methacrylate) (PMMA), and crosslinked poly(4-vinylphenol) (c-PVP), which are commonly used as gate dielectric in flexible electronic applications. The credibility of the transfer process with precise spatial positioning on the target substrate leads to fabrication of freely suspended reduced graphene oxide membrane towards nanoelectromechanical systems (NEMS) based devices such as nanomechanical drum resonators.

Lanthanum Doping in Zinc Oxide for Highly Reliable Thin-Film Transistors on Flexible Substrates by Spray Pyrolysis.

Solution-processed metal-oxide thin-film transistors (TFTs) are considered as one of the most favorable devices for next-generation, large-area flexible electronics. In this paper, we demonstrate the excellent material properties of lanthanum-zinc oxide (LaZnO) thin films deposited by spray pyrolysis and their application to TFTs. The threshold voltage of the LaZnO TFTs shifts toward positive gate voltage, and the mobility decreases with increasing lanthanum ratio in ZnO from 0 to 20%. The purification of the LaZnO precursor (P-LaZnO) further improves the device performance. The P-LaZnO TFT exhibits a field-effect mobility of 22.43 cm2 V-1 s-1, zero hysteresis voltage, and negligible threshold voltage VTH shift under positive bias temperature stress. The enhancement in the electrical properties is due to a decrease in grain size, smooth surface roughness, and reduction in the trap density in the LaZnO film. X-ray photoelectron spectroscopy (XPS) results confirm the presence of La in the TFT channel and at/near the interface of the LaZnO and ZrOx gate insulator, leading to fewer interfacial traps. The flexible P-LaZnO TFT fabricated on the polyimide substrate exhibits a mobility of 17.64 cm2 V-1 s-1 and a negligible VTH shift under bias stress. Also, the inverter made of LZO TFTs is working well with a voltage gain of 17.74 (V/V) at 4 V. Therefore, the LaZnO TFT is a promising device for next-generation flexible displays.

Facile large-area uniform photolithography of membrane diffractive lens based on vacuum assisted self contact method

Optical polyimide (PI) membrane is a promising substrate material for diffractive lens applied in future large-aperture space based imaging system because of its light weight, environmental adaptability and deployable feature. In this letter, we put forward a facile large-area uniform photolithography technique using vacuum assisted self contact method to fabricate large-aperture membrane diffractive lens. We fabricated a φ 400 mm aperture membrane off-axis 2-levels Fresnel Zone Lens (FZL) based on the method and achieved uniformly distributed photoresist morphology as well as over 36.6% average diffraction efficiency in full aperture. The results demonstrated that vacuum assisted self contact method effectively eliminates considerable air gaps caused by unevenness of large area photomask and substrate, thus facilitates uniform light field distribution in photoresist. This work provides reference to fabrication techniques of large aperture membrane diffractive lens, and offers feasible methods for future large area flexible electronics manufacturing.

The Effect of Torsional Bending on Reliability and Lifetime of Printed Silver Conductors

Capability of high-speed and low-cost manufacturing makes the printing techniques a very promising approach for large-area flexible electronics mass manufacturing. Due to fast and intensive technology development, the lack of knowledge about the reliability and lifetime of printed electronics is obvious, requiring further investigation. Especially, the effect of torsional bending on lifetime is a mostly unexplored field of reliability testing. In this article, a torsional bending test of parallel printed silver conductors (0.3-, 0.5-mm pitch) on polymer substrate (polyethylene terephthalate, 125- $\mu \text{m}$ thickness) was conducted and analyzed. According to the experimental results, torsional bending causes wear-out type failures in conductors and the length-to-width (LTW) ratio of the sample’s substrate was observed to have a significant impact on reliability. If the LTW ratio is smaller than 3, the lifetime of printed conductor seems to collapse and samples lasted for approximately only 17 bending cycles on average. Lifetime was improved by increasing the LTW ratio and samples withstood over hundreds of cycles with LTW ratio of higher than 15. However, the distance of a conductor from the edge of the substrate was not observed to have any significant influence on the reliability under torsional bending.

Aerosol jet printing of PEDOT:PSS for large area flexible electronics

We investigate and optimize the Aerosol Jet Printing of PEDOT:PSS by studying the role of parameters determining the final quality of the printed features. Printing thin films of organic materials requires a high control in the deposition process to control the morphology/structure of the films that determine the electrical and functional performance of organic devices. We studied aerosol jet printed lines of the PEDOT:PSS semiconductive polymer on flexible Kapton substrates. We choose the focus ratio, defined as the ratio between the sheath and carrier gas flow rates, as the main parameter that best characterizes the process and hence the characteristics of printed lines. A detailed analysis of the line width and thickness, as a function of the focus ratio and carrier gas flow for different nozzle sizes and sheath gas flow rates, is reported. The edge profile definition of printed PEDOT:PSS lines has been found to be affected by a combination of overspray, typical of aerosol deposition, and pinholes due to the Kapton/PEDOT:PSS interaction, while their core profile results to be almost defects free. An optimal printing window for different nozzle sizes has been determined in terms of a minimization of overspray/pinholes effects with respect to the whole line width. Finally, an array of whole-plastic, planar Organic Electrochemical Transistors, having both the channel and the gate electrode made of PEDOT:PSS, has been manufactured using the best combination of process parameters. Transistors have been characterized for different channel/gate area ratios and the transconductance analysed as a function of channel to gate area.

Printed carbon nanotube thin-film transistors: progress on printable materials and the path to applications.

Printing technologies have attracted significant attention owing to their potential use in the low-cost manufacturing of custom or large-area flexible electronics. Among the many printable electronic materials that have been explored, semiconducting carbon nanotubes (CNTs) have shown increasing promise based on their exceptional electrical and mechanical properties, relative stability in air, and compatibility with several printing techniques to form semiconducting thin films. These attractive attributes make printed CNT thin films promising for applications including, but not limited to, sensors and display backplanes - at the heart of which is electronics' most versatile device: the transistor. In this review, we present a summary of recent advancements in the field of printed carbon nanotube thin-film transistors (CNT-TFTs). In addition to an introduction of different printing techniques, together with their strengths and limitations, we discuss key aspects of ink/material selection and processing of various device components, including the CNT channels, contacts, and gate insulators. It is clear that printed CNT-TFTs are rapidly advancing, but there remain challenges, which are discussed along with current techniques to resolve them and future developments towards practical applications from these devices. There has been interest in low-cost, printable transistors for many years and the CNT-TFTs show great promise for delivering, but will not become a reality without further research advancement.

Contact line curvature-induced molecular misorientation of a surface energy patterned organic semiconductor in meniscus-guided coating

The printing of organic semiconductors (OSCs) by means of meniscus guided coating (MGC) has great potential for the fabrication of high-performance, uniform, and large area flexible electronics. Furthermore, surface energy patterning allows low-cost, large area manufacturing, and is a requirement for device isolation to achieve accurate drive and to minimize power consumption. We investigated the morphological and electrical characteristics of surface energy patterned OSCs coated using the MGC method. A unique phenomenon, contact line curvature-induced molecular misorientation effect, which occurs in the patterning of OSCs with the MGC method, is demonstrated. This effect is highly dependent on the pattern width which decided contact line curvature. It influences the charge transport properties and hence the field-effect mobility of organic thin-film transistors (OTFTs). OTFTs in widths ranging from 50 to 500 µm were fabricated. The highest misorientation angle was induced in the 50 µm pattern width and the corresponding OTFTs exhibited the highest mobility.

Liquid Metal Droplet and Graphene Co-Fillers for Electrically Conductive Flexible Composites.

Colloidal liquid metal alloys of gallium, with melting points below room temperature, are potential candidates for creating electrically conductive and flexible composites. However, inclusion of liquid metal micro- and nanodroplets into soft polymeric matrices requires a harsh auxiliary mechanical pressing to rupture the droplets to establish continuous pathways for high electrical conductivity. However, such a destructive strategy reduces the integrity of the composites. Here, this problem is solved by incorporating small loading of nonfunctionalized graphene flakes into the composites. The flakes introduce cavities that are filled with liquid metal after only relatively mild press-rolling (<0.1 MPa) to form electrically conductive continuous pathways within the polymeric matrix, while maintaining the integrity and flexibility of the composites. The composites are characterized to show that even very low graphene loadings (≈0.6 wt%) can achieve high electrical conductivity. The electrical conductance remains nearly constant, with changes less than 0.5%, even under a relatively high applied pressure of >30 kPa. The composites are used for forming flexible electrically-conductive tracks in electronic circuits with a self-healing property. The demonstrated application of co-fillers, together with liquid metal droplets, can be used for establishing electrically-conductive printable-composite tracks for future large-area flexible electronics.

Printed flexible thin-film transistors based on different types of modified liquid metal with good mobility

High-performance logic circuits fabricated on flexible or unconventional substrates have become a necessity for several new applications. Generally, compared to those fabricated on more rigid substrates, printed, large-area, and flexible thin film transistors (TFTs) are prone to under-performance, which severely limits their practical value. The realization of printed flexible macroelectronics requires advancements in material science and novel fabricating techniques. In this study, using a fast printing process, we manufacture liquid metal-carbon nanotube TFTs on a thin polyethylene terephthalate substrate. These flexible TFTs (p-type) exhibit enhance stability and flexibility, carrier mobility (10.61 ${\rm~cm}^2{\rm~V}^{-1}{\rm~s}^{-1}$), and transconductance (0.88 $\mu$S). Furthermore, we realize dependable n-type and ambipolar transistors based on liquid metals with charge transport efficiencies that are comparable to our p-type counterparts, thus providing a foundation for manufacturing integrated circuits and complementary logic gates on flexible substrates. This study shows the positive progress of liquid metal printing-enabled functional devices and discusses the possibility of practical applications; moreover, it sets the foundation for printed high-performance and large-area flexible liquid metal electronics.