Land Grid Array Package Research Articles

Validation of New Substrate Design for the Improvement of Strip Warpage on LGA Packages

Land grid array or LGA package of semiconductor has been commonly used on our modern technology, from home gadgets up to industrial uses. Improvements to correct product defects and process issues are introduced to have quality products for customer satisfaction. Substrate warpage have been affecting production performance on semiconductor manufacturing. The unacceptable response results to loss of productivity losses and yield detraction. Different process improvements have been experimented to contain the problem, but results are not maintained and found to be not robust. This is where design innovation plays the part. Solder mask opening on the base material of the substrate is considered to have a favorable response after subjecting it to different environment conditions. From fast indexing and machine movement up to high thermal application on oven curing, having a robust solder mask design makes the unit acceptable and with quality. Product design as mentioned takes on another level to address the phenomenon of substrate warpage. This manuscript will be discussing how the solder mask of the substrate is optimized to achieved minimal or zero substrate warpage by performing different experiments on process and the product itself. Statistical analysis has been the basis for the implementation of the newly validated substrate design.

Design and fabrication of a ceramic land grid array package for power supply circuits

The popularity of electronic devices used in a wide variety of applications have significantly increased, as a result, more and more power supplies are needed urgently. In this paper, a ceramic land grid array package for power supply circuits is designed. Unlike conventional low temperature co-fired ceramic and plastic power supply packages, which exhibited many problems in deposit and long-time employment, a structure with superior properties using materials of alumina ceramic and tungsten is proposed. Theoretical analysis, finite element simulation and experimental research are applied to help package design. On the basis of high temperature co-fired ceramic technique, package specimens are also fabricated. Finally, several kinds of tests, including conductivity resistance, current carrying capability, temperature cycling test and gas leakage are carried out to evaluate the performance and reliability of packages. Experiment results indicate that all packages are qualified. Our fabricated packages are able to support 10 A load without experiencing property damage or deterioration. After temperature cycling within -65 °C ∼ +125 °C, 100 heating-cooling cycles, subsequently, the gas leak rates of all specimens are detected with values are not higher than 1 × 10−3 Pa·cm3/s. Moreover, there is no appearance quality defect can be observed by 20 × microscopy at the end of tests. Performance and reliability of the fabricated package samples meet requirements set out in the application.

Die Placement Advancement for Prevention of Silhouetted Die Occurrence on LGA Package

In semiconductor packaging industry, silhouetted die defect is occasionally encountered in singulation process esp. on substrate land grid array (LGA) package with tight clearances. This paper is focused on the prevention of the silhouetted die occurrence as it would affect the assembly yield performance of the device. The silhouetted die is caused by the tight clearance of die edge to package edge, given the machine and process tolerances. Process enhancement and optimization were done through adjusting the die placement accordingly as per the defined measurement. Eventually, the occurrence of silhouetted die was successfully mitigated by formulating the appropriate die placement references.

Structural Design of Land Grid Array Loading Mechanisms for Intel Central Processor Unit Stack Retention

For more than a decade, land grid array (LGA) has been one of the main central processor unit (CPU) packages developed at Intel and AMD, and widely used in different computer systems. LGA loading mechanism has become more critical to achieve mechanical, thermal, and electrical functions with the increasing retention force requirement. During the development of the loading mechanisms for LGA packages and sockets, socket pin contact to LGA pad under retention load, solder joint reliability under shock load, socket pin fretting under vibration, and load degradation are some of the key structural risks. This paper reviews the structural designs of different loading mechanism solutions systematically and summarizes the key structural concerns and advantages. While the finite element analysis (FEA) was used to guide the design options in early platform architectural definition, this review discusses the evolution of Xeon LGA loading mechanisms developed at the Intel Data Center Group.

FcLGA Package Assembly Qualification for Mobile Applications

Abstract Flip Chip Land Grid Array (FcLGA) packages are widely used in Mobile product applications due to their thin form factor and performance. Assembly process qualification requires careful selection of materials and optimization of reflow processes to make consistent and reliable product. The fcLGA typically uses an organic substrate on which the die is reflowed instead of the copper lead frame used in QFN packages. This requires assessment of CTE mismatch and controlled reflow processes to prevent bump separation [1]. The paper reviews the selection of substrate, optimization of assembly process and reliability testing conducted for package qualification

Solder paste volume effects on assembly yield and reliability for bottom terminated components

PurposeSolder paste printing is the most common method for attaching surface mount devices to printed circuit boards (PCB), and it has been reported that a majority of all assembly defects occur during the stencil printing process. It is also recognized that the solder paste printing process is wholly responsible for the solder joint formation of leadless package technologies such as land grid array (LGA) and quad-flat no-lead (QFN) components and therefore is a determining factor in the long-term reliability of said devices. The aim of this experiment is to determine the acceptable lower limit for solder paste volume deposit tolerances during stencil printing process to ensure both good assembly yield and reliability expectations.Design/methodology/approachStencils with modified aperture dimensions at particular locations for LGA and QFN package footprints were designed to vary the solder paste volume deposited during the stencil printing process. Solder paste volumes were measured using solder paste inspection system. Low volume solder paste deposits were generated using the modified stencil designs to evaluate assemble yield. Accelerated thermal cycling (ATC) was used to determine the reliability of the solder joints. Failure analysis was used to determine if the failure was attributed to the low paste volume locations.FindingsSolder joints formed with nominal paste volume survived longer in ATC compared to intentionally low volume joints. Transfer efficiency numbers for both good assembly yield and good reliability are reported for LGA and QFN devices. A lower volume limit is reported for leadless devices that should not significantly affect yield and reliability in thermal cycling.Originality/valueVery little literature is available on solder paste volume tolerance limits in terms of assembly yield and reliability. Manufacturers often use ±50 or ±30 per cent of stencil aperture volume with no evidence of its effectiveness in determining yield and reliability of the solder joints.

In-situ investigation of EMC relaxation behavior using piezoresistive stress sensor

The relaxation behavior of an epoxy molding compound (EMC) subjected to a constant strain can cause new reliability challenges in automotive electronics. This problem will be exacerbated due to the ever-increasing demand in modern electronics systems for miniaturization with more functionality, yet it has not been studied extensively to mitigate its effect on reliability. In this study, a piezoresistive silicon-based stress sensor is used to understand the stress state in an electronic control unit (ECU), more specifically the relaxation behavior of EMC caused by the storage time of an ECU (i.e., duration between production and actual usage). Mechanical stresses are measured by the piezoresistive stress sensor that is encapsulated in a standard microelectronic 3×3mm land grid array (LGA) package. The relaxation behavior is observed at three different temperatures for 1week: 75°C, 100°C and 125°C. The relaxation behavior is measured continuously for one more week after cooling the package to room temperature (at 25°C). An additional test is conducted at 85°C with 85% relative humidity to investigate the effect of moisture diffusion on the package. The experimental results clearly indicate that the proposed approach can be used for better understanding of the evolution of stresses in molded packages during their lifetime, especially during storage, which in turn can lead to more optimal designs in the future.

A reliable solderless connection technique for high I/O counts ceramic land grid array package for space applications

Area Array microelectronic package with small pitch and large I/O counts is now widely used in the ceramic packaging of microelectronics Integrated Circuit (IC). This kind of Land Grid Array (LGA) device cannot be directly soldered on Printed Circuit Board (PCB). In order to mount them on PCB the LGA device back end is mostly terminated with solder columns (CGA device) or with solder balls (BGA device). For space application CGA and BGA ceramic devices are prone to early failure due to harsh environment. Indeed vibration and shock during launch as well as thermal cycling in orbit induces a high level of stress in the solder joints between board and device. Such high level of stress can ultimately cause the failure of one of the solder joints causing permanent functional electrical failure. As the trend for next generation of ceramic IC device is to increase their sizes and their density of I/O, susceptibility to mechanical and thermal loading grows even more. This statement is in contradiction with the high level of reliability required for space application. To overcome this situation CNES has taken the lead with space users and space connector manufacturers to develop for space application a reliable solderless solution that will enable to easily mount on board the actual and the next generation of ceramic IC package. This solderless solution consists in using a thin connector interposer between the ceramic LGA device and the board. A clamping system is used to hold and keep aligned on the board the stacking composed of the ceramic device and the interposer connector. This solderless solution has been evaluated according to the European space standard and has demonstrated a high robustness to harsh environment making this solution compliant for space application.

Nondestructive Evaluation of Poor-Wetted Lead-Free Solder Bumps in Ball Grid Array Packages Using Laser Ultrasound and Interferometric Technique

A laser ultrasound and interferometer inspection system has been successfully applied to detect solder bump defects, including missing, misaligned, open, and cracked solder bumps in flip chips, land grid array packages and chip capacitors. This system uses a pulsed Nd:YAG laser to induce ultrasound in the chip packages in the thermoelastic regime; it then measures the transient out-of-plane displacement response on the package surface using a laser interferometer. The amplitudes of the out-of-plane displacement responses are usually in the order of nanometer. The quality of solder bumps is evaluated by analyzing the transient responses. In this paper, this system is used to evaluate the quality of lead-free solder bumps in ball grid array (BGA) packages; specifically, BGA packages with poor wetted solder bumps are used as test vehicles. Poor wetting not only decreases the mechanical strength of interconnection at the interface between the solder bumps and substrate, but also deteriorates electrical and thermal performance because of the unreliable connections between the package and the printed circuit board (PCB). Causes of poor wetting vary from the solder materials themselves to the manufacturing process. Here, poor wetting of solder bumps were intentionally created by using an improper reflow profile. The transient out-of-plane displacement signal responses from these packages are compared to a hybrid reference signal generated by signal responses from defect-free samples. Packages with poor wetted solder bumps are distinguished from the normal packages by using the correlation coefficient signal analysis method. Then, laser ultrasound inspection results are also compared with results from continuity test, X-ray inspection and scanning acoustic microscope (SAM). Finally, the cross-section images are further used to confirm the existence of the poor wetting in samples with unusual correlation coefficient. It can be concluded that this laser-ultrasound system is capable of identifying the presence of poor wetting in BGA packages.

Drop Performance of Land Grid Array Packages as a Function of Cu Content in Lead-free Solder Alloys

High strain-rate drop impact tests were performed for land grid array (LGA) packages with (electroless nickel immersion gold) ENIG metallization and lead-free solder interconnects. Sn-4Ag-0.5Cu (in wt%, SAC405), Sn-3.5Ag (in wt%), and Sn-0.7Cu (in wt%) were used for pretinning the LGA pads. SAC 405 alloy was used for the LGA-to-board mounting. Drop test results showed two distinct trends. Samples pretinned with Sn-4Ag-0.5Cu and Sn-3.5Ag showed poor drop performance while those pretinned with Sn-0.7Cu (in wt%) or without pretinning showed excellent drop performance. The dierence in behavior is related to the initial intermetallic morphology and structure. The needle shape Ni3Sn4-based intermetallics were observed for the first two cases. This led to poor adhesion between solder and NiP metallization. The samples with Sn-0.7Cu pretinning and no pretinning showed a continuous intermetallic morphology. In this case, sucient Cu improved the solder wetting and formed a continuous intermetallic morphology, leading to better drop performance. A sucient amount of Cu makes the better wetting, forming (Cu,Ni)

Low-Loss Chip-to-Chip Optical Interconnection Using Multichip Optoelectronic Package With 40-Gb/s Optical I/O for Computer Applications

We have developed novel optoelectronic packages and optical transmission system using an optical connector with an external optical waveguide to achieve low-loss chip-to-chip optical interconnections for computer systems. In order to connect the package and the connector, we have also proposed a socket as a coupling structure to realize an all passive alignment and high coupling efficiency. We have demonstrated high-speed and error-free signal transmission with four channels at 10-Gb/s/ch and up to 12-Gb/s/ch. Optical input and output (I/O) interfaces, including optical devices and controller integrated circuits (ICs), have been constructed onto the package surface by conventional flip-chip mounting. The optoelectronic package has optical waveguide holes (OWGHs) to pass optical signal vertically from a vertical-cavity surface-emitting laser (VCSEL) and to a photodiode (PD). The OWGHs consist of core and cladding material to enhance optical confinement. The optical connector that is just set underneath the package with two guide pins contains the thin-film polymer waveguide with 45°-ended mirrors to bend the optical signal. Therefore, the shorter optical coupling distance has achieved low-loss optical link without microlenses between packages. We have also proposed an alignment structure to easily enable passive alignment, which is based on existing land grid array (LGA) packages and sockets clamping structures to simultaneously improve cost-competitiveness and usability.

Board-Level Solder Joint Reliability Study of Land Grid Array Packages for RF Application Using a Laser Ultrasound Inspection System

Microelectronics packaging technology has evolved from through-hole, and bulk configuration to surface-mount, and small-profile ones. Today’s electronics industry is also transiting from SnPb to Pb-free to meet environmental requirements. Land grid array (LGA) package has been becoming popular in portable electronics in terms of low profile on the printed wiring boards and direct Pb-free assembly process compatibility. With the package profile shrinking and operating power increasing, solder joint quality and reliability has become a major concern in microelectronics manufacturing. The solder joint failure at the package level or board level will cause electronic devices not to function during service. In this paper, board-level solder joint reliability of the LGA packages under thermal loading is studied through thermal cycling tests. A novel laser ultrasound-interferometric system developed by the authors is applied to inspect solder joint quality during the thermal cycling tests. While the laser ultrasound inspection technique has been successfully applied to flip chips and chip scale packages, this study is the first application of this technique to overmolded packages. In this study, it is found out that the LGA packages can withstand 1000 temperature cycles without showing crack initiation or other failure mechanisms in the solder joints. The laser ultrasound inspection results match the visual observation and X-ray inspection results. This study demonstrates the feasibility of this system to solder joint quality inspection of overmolded packages. In particular, the devices constituting the objective of this study are radio frequency modules, which are encapsulated through overmolding and are mounted on a typical four-layer FR4 board through LGA terminations.

Reliability Assessment of Land Grid Array Sockets Subjected to Mixed Flowing Gas Environment

Land grid array (LGA) sockets are used as separable interconnects between printed circuit boards, and high I/O integrated circuit components. Because the socket contacts with the component and the circuit board on both sides, low and stable contact resistances among these interfaces are desirable for the reliable electrical connection of the LGA package. This paper compares the contact resistance degradation of two LGA socket designs, silver particles in an elastomer column, and silver-plated-nickel in an elastomer film, subjected to accelerated corrosion environment, or so-called mixed flowing gases (MFG). Increased contact resistance was observed in the sockets due to corrosion products over the contact surface after metal corrosion. Corrosion products were analysed using environmental scanning electron microscopy (E-SEM), energy dispersive spectroscopy (EDS), and x-ray photoelectron spectroscopy (XPS). AgCl, Aga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O, and Ag <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> SO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> were identified after silver corrosion; NiCl <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , Ni <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> SO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> , and MS were found after Ni corrosion. The nickel corrosion product bridged the adjacent contacts as whiskers with time. The lifetime can be estimated by an acceleration factor: two day MFG Battelle Class II exposure equals one year of field service. The shelf life of conductive elastomer LGA sockets is expected to be longer than five years.

A chip-scale packaging technology for 60-GHz wireless chipsets

In this paper, we present a cost-effective chip-scale packaging solution for a 60-GHz industrial-scientific-medical band receiver (Rx) and transmitter (Tx) chipset capable of gigabit-per-second wireless communications. Envisioned applications of the packaged chipset include 1-3-Gb/s directional links using amplitude shift-keying or phase shift-keying modulation and 500-Mb/s-1-Gb/s omni-directional links using orthogonal frequency-division multiplexing modulation. This paper demonstrates the first fully package-integrated 60-GHz chipset including receive and transmit antennas in a cost-effective plastic package. A direct-chip-attach (DCA) and surface mountable land-grid-array (LGA) package technology is presented. The size of the DCA package is 7/spl times/11 mm/sup 2/ and the LGA package size is 6/spl times/13 mm/sup 2/. Optionally, the Tx and Rx chip can be packaged together with Tx and Rx antennas in a combined 13/spl times/13 mm/sup 2/ LGA transceiver package.

Circuit model of microstrip patch antenna on ceramic land grid array package for antenna-chip codesign of highly integrated RF transceivers

This paper presents the circuit model of a microstrip patch antenna on a ceramic land grid array (CLGA) package for the antenna-chip codesign of a highly integrated radio-frequency (RF) transceiver. The microstrip patch antenna is fed by packaging interconnect components such as bond wires, signal traces, and vias in a ground-signal-ground (G-S-G) configuration from the carried chip. The circuit model that consists of RLC lumped elements of both microstrip patch antenna and feeding interconnect components has been developed with an emphasis on verifying existing or deriving analytical formulas. The RLC values of the microstrip patch antenna are calculated with our improvements to existing computer-aided design formulas, while the RLC values of the feeding interconnect components are calculated with more efforts. In particular the C values related to the vias and signal traces require to be calculated numerically and they are calculated here with the method of moments and the conformal mapping method, respectively. The circuit model is validated with numerical simulations (High Frequency Structure Simulator) and network analyzer measurements.

Characterization and Modeling of Printed Wiring Board Warpage and its Effect on LGA Separable Interconnects

The paper presents a study on printed wiring board (PWB) warpage caused by the mechanical fastening of separable interconnects, known as land grid array (LGA) package assemblies. Out-of-plane displacement of the PWB were measured and characterized, as well as force-per-pin values of the LGA, and correlations were made between the two. Classical laminate theory was utilized to describe the warpage behavior of the assembly and a model was presented to solve the out-of-plane displacements. An overall assessment of the assembly was made and compared to the mechanical specification of the LGA.

Materials characterization of the effect of mechanical bending on area array package interconnects

The mechanical integrity of solder joint interconnects in PWB assemblies with micro-BGA, chip scale, and land grid array packages is being questioned as the size and pitch decrease. Some consumer products manufacturers have mechanically reinforced fine pitch package interconnects with an adhesive underfill, and others are evaluating the need for underfill on a case-by-case basis. Three-point cyclic bend testing provides a useful tool for characterizing the expected mechanical cycling fatigue reliability of PWB assemblies. Cyclic bend testing is useful for characterizing bending issues in electronic assemblies such as repetitive keypad actuation in cell phone products. This paper presents the results of three-point bend testing of PWB assemblies with fine pitch packages. The solder joints on ceramic components performed better than a laminate interposer component in bend testing, because of the stiffening effect of the ceramic packaging materials. The methodology of materials analyses of the metallurgy of solder interconnects following mechanical bending and thermal cycle testing is described. The microstructure and fracture surfaces of solder joint failures in bend test samples differed significantly from thermal cycle test samples.

Assessing the operating reliability of land grid array elastomer sockets

The contact resistances of 2300 elastomer button contacts used for LGA (land grid array) package interconnections were measured over a range of contact loads. The experimental data, fitted using three probability distribution functions, show that an inverse Gaussian distribution best describes elastomer button contact resistance behavior. Using this probability function, the minimum operating contact load necessary for a desired socket operating reliability can be determined.

A 650-MHz, IA-32 microprocessor with enhanced data streaming for graphics and video

This paper describes a new IA-32 architecture microprocessor that implements 70 additional instructions to further accelerate the performance of data-streaming applications such as three-dimensional graphics and video encode/decode. This processor is an enhancement over the previous implementation of this family through the addition of these new instructions along with circuit improvements in several key areas for higher clock frequency. The 10.17/spl times/12.10 mm/sup 2/ die contains 9.5 million transistors and is fabricated in a CMOS five-layer-metal 0.25-/spl mu/m process with a six-layer organic land grid array package using C4 interconnect technology. It has an operating range of 1.4-2.2 V and is currently running up to 650 MHz.

AIN LGAs for High Performance Packaging Applications

Because they offer many properties favourable for IC package construction, ceramics have been in widespread use as an electronic package material since the early 1960s. In recent years, with trends towards higher speed semiconductors generating up to 30‐40 watts power, packaging materials must possess excellent thermal, electrical and mechanical properties. Aluminium nitride, with a thermal conductivity of 170 W/m.K., high fracture strength and a thermal coefficient of expansion match with silicon, has been used to manufacture multilayer LGA (land grid array) packages for high performance applications. A 725 AIN LGA has been manufactured and its performance characteristics have been compared with those of an alumina (with copper/tungsten slug) packaging alternative. Because of the high thermal conductivity of aluminium nitride, all designs can be made in a cavity‐up configuration, resulting in significant package body size reduction. The area under the cavity can be used for increasing I/O number and a ground plane can be inserted under the cavity, reducing simultaneous switching noise. Aluminium nitride is particularly beneficial for flip‐chip interconnection. Its close TCE match to silicon eliminates the stress reduction requirement for die underfill.