L2 Cache Research Articles

Towards Analysing Cache-Related Preemption Delay in Non-Inclusive Cache Hierarchies

The impact of preemptions has to be considered when determining the schedulability of a task set in a preemptively scheduled system. In particular, the contents of caches can be disturbed by a preemption, thus creating context-switching costs. These context-switching costs occur when a preempted task needs to reload data from memory after a preemption. The additional delay created by this effect is termed cache-related preemption delay (CRPD). The analysis of CRPD has been extensively studied for single-level caches in the past. However, for two-level caches, the analysis of CRPD is still an emerging area of research. In contrast to a single-level cache, which is only affected by direct preemption effects, the second-level cache in a two-level hierarchy can be subject to indirect interference after a preemption. Accesses that could be served from the L1 cache in the absence of preemptions, may be forwarded to the L2 cache, as the relevant data was evicted by a preemption. These accesses create the indirect interference in the L2 cache and can cause further evictions. Recently, a CRPD analysis for two-level non-inclusive cache hierarchies was proposed. In this article, we show that this state-of-the-art analysis is unsafe as it potentially underestimates the CRPD. Furthermore, we show that the analysis is pessimistic and can overestimate the indirect preemption effects. To address these issues, we propose a novel analysis approach for the CRPD in a two-level non-inclusive cache hierarchy. We prove the correctness of the presented approach based on the set of feasible program execution traces. We implemented the presented approach in a worst-case execution time (WCET) analysis tool and compared the performance to existing analysis methods. Our evaluation shows that the presented analysis increases task set schedulability by up to 14 percentage points compared with the state-of-the-art analysis.

Asynchronous Memory Access Unit: Exploiting Massive Parallelism for Far Memory Access

The growing memory demands of modern applications have driven the adoption of far memory technologies in data centers to provide cost-effective, high-capacity memory solutions. However, far memory presents new performance challenges because its access latencies are significantly longer and more variable than local DRAM. For applications to achieve acceptable performance on far memory, a high degree of memory-level parallelism (MLP) is needed to tolerate the long access latency. While modern out-of-order processors are capable of exploiting a certain degree of MLP, they are constrained by resource limitations and hardware complexity. The key obstacle is the synchronous memory access semantics of traditional load/store instructions, which occupy critical hardware resources for a long time. The longer far memory latencies exacerbate this limitation. This article proposes a set of Asynchronous Memory Access Instructions (AMI) and its supporting function unit, Asynchronous Memory Access Unit (AMU), inside contemporary Out-of-Order Core. AMI separates memory request issuing from response handling to reduce resource occupation. Additionally, AMU architecture supports up to several hundreds of asynchronous memory requests through re-purposing a portion of L2 Cache as scratchpad memory (SPM) to provide sufficient temporal storage. Together with a coroutine-based programming framework, this scheme can achieve significantly higher MLP for hiding far memory latencies. Evaluation with a cycle-accurate simulation shows AMI achieves 2.42× speedup on average for memory-bound benchmarks with 1μs additional far memory latency. Over 130 outstanding requests are supported with 26.86× speedup for GUPS (random access) with 5 μs latency. These demonstrate how the techniques tackle far memory performance impacts through explicit MLP expression and latency adaptation.

Memory architecture to mitigate side channel attacks for cryptographic application using loop cut technique

Cryptography is crucial in embedded systems for safeguarding sensitive information, maintaining data integrity, and facilitating secure communication. L1 cache memory enhances overall performance by temporarily storing cryptographic keys. Post-quantum cryptography (PQC) focuses on creating algorithms that stay secure even against quantum computing threats. However, PQC doesn't fully protect against side-channel attacks (SCA). As IoT devices like wearable health monitors and industrial sensors become more widespread, the demand for lightweight cryptography increases to balance security with resource constraints. Yet, lightweight cryptography can face challenges, including reduced security and increased susceptibility to SCA due to smaller key sizes. Attackers can exploit power consumption patterns through side-channel attacks (SCA), such as Power Analysis, to extract these secret keys. Once a key is compromised, encrypted data becomes vulnerable. In cloud computing cache side-channel attacks take advantage of multiple virtual machines running simultaneously on the same hardware, enabling them to extract sensitive information from encryption processes. Although many SRAM cells have been designed in the literature, none offer complete security against SCA. This paper presents a new architecture for secure cache memory using a proposed 10T SRAM cell that secures all three cell operations (read, write, and hold) against SCA attacks. Additionally, this architecture also prevents half selection issue in cache memory. The security measure of proposed-10T cell is 97.19 % which is highest among all other cells and reliability measure is 82.03 %.The cell also offers highest hold stability of 421 mV along with good read stability and write ability of 220 mV and 334 mV respectively. The leakage of Proposed-10T cell is also less i.e., 13.56 pA. The Performance and Security Factor (PSF) is computed for all considered cells, encompassing various performance and security metrics. The normalized PSF (PSF)N of the Proposed-10T cell is 2.17, the highest among all cells considered for comparison. Therefore, the Proposed-10T cell architecture is fully secure against SCA and achieves better performance during cell operations.

ATA-Cache: Contention Mitigation for GPU Shared L1 Cache With Aggregated Tag Array

ATA-Cache: Contention Mitigation for GPU Shared L1 Cache With Aggregated Tag Array

Cross-Core Data Sharing for Energy-Efficient GPUs

Graphics Processing Units (GPUs) are the accelerator of choice in a variety of application domains because they can accelerate massively parallel workloads and can be easily programmed using general-purpose programming frameworks such as CUDA and OpenCL. Each Streaming Multiprocessor (SM) contains an L1 data cache (L1D) to exploit the locality in data accesses. L1D misses are costly for GPUs due to two reasons. First, L1D misses consume a lot of energy as they need to access the L2 cache (L2) via an on-chip network and the off-chip DRAM in case of L2 misses. Second, L1D misses impose performance overhead if the GPU does not have enough active warps to hide the long memory access latency. We observe that threads running on different SMs share 55% of the data they read from the memory. Unfortunately, as the L1Ds are in the non-coherent memory domain, each SM independently fetches data from the L2 or the off-chip memory into its L1D, even though the data may be currently available in the L1D of another SM. Our goal is to service L1D read misses via other SMs, as much as possible, to cut down costly accesses to the L2 or the off-chip DRAM. To this end, we propose a new data sharing mechanism, called Cross-Core Data Sharing (CCDS) . CCDS employs a predictor to estimate whether or not the required cache block exists in another SM. If the block is predicted to exist in another SM’s L1D, CCDS fetches the data from the L1D that contains the block. Our experiments on a suite of 26 workloads show that CCDS improves average energy and performance by 1.30 × and 1.20 ×, respectively, compared to the baseline GPU. Compared to the state-of-the-art data-sharing mechanism, CCDS improves average energy and performance by 1.37 × and 1.11 ×, respectively.

FDRA: A Framework for a Dynamically Reconfigurable Accelerator Supporting Multi-Level Parallelism

Coarse-grained reconfigurable architectures (CGRAs) have emerged as promising accelerators due to their high flexibility and energy efficiency. However, existing open source works often lack integration of CGRAs with CPU systems and corresponding toolchains. Moreover, there is rare support for the accelerator instruction pipelining to overlap data communication, computation, and configuration across multiple tasks. In this article, we propose FDRA, an open source exploration framework for a heterogeneous system-on-chip (SoC) with a RISC-V processor and a dynamically reconfigurable accelerator (DRA) supporting loop, instruction, and task levels of parallelism. FDRA encompasses parameterized SoC modeling, Verilog generation, source-to-source application code transformation using frontend and DRA compilers, SoC simulation, and FPGA prototyping. FDRA incorporates the extraction of periodic accumulative operators and multi-dimensional linear load/store operators from nested loops. The DRA enables accessing the shared L2 cache with virtual addresses and supports direct memory access with arbitrary start addresses and data lengths. Integrated into the RISC-V Rocket SoC, our DRA achieves a remarkable 55× acceleration for loop kernels and improves energy efficiency by 29×. Compared to state-of-the-art RISC-V vector units, our DRA demonstrates a 2.9× speed improvement and 3.5× greater energy efficiency. In contrast to previous CGRA+RISC-V SoCs, our SoC achieves a minimum speedup of 5.2×.

Investigation of the Effectiveness of Programs Optimization Methods for Parallel Computing Systems with GPU

Objective. The paper defines the relevance of the task of increasing the efficiency of software, which in this case is understood as reducing the operating time of the designed software in the process of solving computationally complex problems. Method. As an example of such a task, the implementation of the singular value decomposition by the Jacobi method is used. This task finds its application in various fields from signal and image processing to artificial intelligence systems. Parallel computing systems equipped with GPU are chosen as the target computing architecture. The paper discusses methods for improving the efficiency of software for target computing architectures using CUDA. Result. The existing analytical models for evaluating the effectiveness of computer programs are described. The influence of various optimizations, such as optimization of data transfers, use of the unified memory system, the number of threads, memory access patterns, and a number of others on the efficiency of the resulting software is considered. The process of optimizing the SVD implementation program is described, the results of computational experiments are presented. Conclusion. As the number of threads increases, performance may increase more than the number of threads. Impact of memory access pattern: When the memory access sequence is optimal, performance improves noticeably. Adjusting the share of memory used for L1 cache and shared memory does not have a significant impact on performance

On Hardware Flexibility and Heterogeneity: A Vision for Monte Carlo Codes on Incoming RISC-V Computing Devices with AI-based Cross Section

As an open-sourced instruction set and being flexible in hardware extension, RISC-V begins its pace to enter the world of high performance computing. One of the distinguished feature of processing units adopting RISC-V is its ability to add custom circuits with special purpose accelerators. As the artificial general intelligence becomes practical, AI accelerators become an indispensable part of computing devices, where RISC-V is a great fit for the CPU to glue accelerators together. A system of chip designed by Alibaba T-head is one of the early chip in the massive production adopting RISC-V CPU, where the CPU, named Xuantie-910, has a high performance design with 128-bit RISC-V vector processing units, which are designed for accelerating AI applications. OpenMC has been adapted to run on Xuantie-910. In the Monte Carlo method for reactor physics, fetching the neutron cross sections is the hotspot that takes the majority of the computational burden. The traditional point-wise cross sections are slow because of memory latency caused by accessing many nonconsecutive memory addresses. An AI model for cross section is hence proposed. With 2.2 KB of runtime size, the smallest in the published work, the data can be fetched entirely in the L1 cache during on-the-fly cross section evaluation through single memory read. The in-house AI model also covers the entire energy range, unlike only the resonance range is supported in previous work. So, the effects from memory latency is minimized. The average relative error in AI modeled U-238 elastic cross section is 0.6% from point-wise cross section. With a modified version of OpenMC on Apple M3 Max, for a VERA pin-cell problem, compared to the point-wise cross section, the adoption of AI modeled cross section reduces the total runtime by 7%, although the runtime for calculating U-238 elastic cross section causes 40% more runtime. The adoption of AI modeled U-238 elastic cross section leads to K-effective 302 pcm higher than the case of adoption of point-wise cross sections. Advantage of AI model has been verified. With AI modeled cross section, the neutron slowing down problems with pure elastic scattering on U-238 has been studied on Xuantie-910. The average relative error in 65,536 group fluxes is about 0.9% from using point-wise cross section. However, with accelerating with the 128-bit vector processing units, the performance degrades by 35%, because of the narrow 64-bit load and store interface to the vector register files. The performance with Al modeled cross section is about 1/4 of the case with point-wise cross sections. In addition, the 1,024-bit width Ara RISC-V vector processing has been used to study the cost of AI modeled cross section evaluation. Being able to access the open-sourced hardware design in SystemVerilog, cycle accurate circuit simulation is performed. Using the vector processing units, the cost is reduced to 65% of the case using scalar instructions. The 128-bit load and store interface to vector processing units is a major contributor to the speeding up. The width of the load and store interface to vector processing units should be the main optimization factor in chip design to accelerate the AI modeled cross section evaluation.

SeedHit: A GPU Friendly Pre-Align Filtering Algorithm.

The amount of genetic data generated by Next Generation Sequencing (NGS) technologies grows faster than Moore's law. This necessitates the development of efficient NGS data processing and analysis algorithms. A filter before the computationally-costly analysis step can significantly reduce the run time of the NGS data analysis. As GPUs are orders of magnitude more powerful than CPUs, this paper proposes a GPU-friendly pre-align filtering algorithm named SeedHit for the fast processing of NGS data. Inspired by BLAST, SeedHit counts seed hits between two sequences to determine their similarity. In SeedHit, a nucleic acid in a gene sequence is presented in binary format. By packaging data and generating a lookup table that fits into the L1 cache, SeedHit is GPU-friendly and high- throughput. Using three 16s rRNA datasets from Greengenes as input SeedHit can reject 84%-89% dissimilar sequence pairs on average when the similarity is 0.9-0.99. The throughput of SeedHit achieved 1T/s (Tera base per second) on 3080 Ti. Compared with the other two GPU-based filtering algorithms, GateKeeper and SneakySnake, SeedHit has the highest rejection rate and throughput. By incorporating SeedHit into our in-house clustering algorithm nGIA, the modified nGIA achieved a 1.6-2.1 times speedup compared to the original version.

Novel CPU cache architecture based on two-dimensional MTJ device with ferromagnetic Fe3GeTe2

With the development of Artificial Intelligence (AI) in recent years, the fields of computer, biology, medicine, and aerospace have demanded higher requirements for the processing and storage of information. In this paper, a novel Magnetic Tunnel Junction (MTJ) based Spin-Orbital Torque Magnetic Random Access Memory (SOT-MRAM) composed of Fe3GeTe2 (FGT) is employed as a storage medium in the computer architecture. On the basis of the analysis of the fundamentals, model configuration, characteristics and performance advantages of the FGT based SOT device, a hybrid storage (L1, L2, Last Level Cache) is constructed, with FGT-SOT-MRAM, conventional SOT-MRAM and STT-MRAM replacing the original static random access memory (SRAM) in the novel triple-level CPU cache architecture. This can override the increasing leakage problem of SRAM, while opening up the application of two-dimensional van der Waals ferromagnets in computer systems at the L1 cache level. Meanwhile, an innovative cache optimization scheme is put forward for magnetic memory to better match the performance of FGT-SOT-MRAM to CPU. The simulation results demonstrate that the FGT-based MRAM can achieve up to 38.03% IPC optimization and 53.41% power optimization in the CPU cache system in contrast to the conventional ones.

CAMP: a hierarchical cache architecture for multi-core mixed criticality processors

CAMP proposes a hierarchical cache subsystem for multi-core mixed criticality processors, focusing on ensuring worst-case execution time (WCET) predictability in automotive applications. It incorporates criticality-aware locked L1 and L2 caches, reconfigurable at mode change intervals, along with criticality-aware last level cache partitioning. Evaluation using CACOSIM, Moola Multicore simulator, and CACTI simulation tools confirms the suitability of CAMP for keeping high-criticality jobs within timing budgets. A practical case study involving an automotive wake-up controller using the sniper v7.2 architecture simulator further validates its usability in real-world mixed criticality applications. CAMP presents a promising cache architecture for optimized multi-core mixed criticality systems.

A study on impacts of hardware changes on performance of different multithreading libraries based on Gem5

This paper presents a thorough investigation into the performance of various multithreading libraries on different hardware configurations utilizing gem5. The study compares the performance of commonly-used multithreading libraries, including OpenMP, Pthread, TBB, and Dlib, through several benchmarks representing distinct types of workloads. Key hardware factors that directly affect the performance of each library are identified and analyzed. The research findings provide valuable insights and recommendations for selecting an appropriate multithreading library for a given application and hardware platform. Results indicate that the performance of multithreading libraries is influenced by numerous hardware factors, such as L1 cache size, L1 cache associate, L1 cache replacement policy, number of threads, and memory type. The libraries respond differently to these factors, and the performance variability of each library depends on the nature of the workload. The study offers a detailed analysis and valuable insights into the effects of these hardware factors on each library. This study contributes by presenting a comprehensive comparison of several widely used multithreading libraries across numerous hardware configurations, identifying the key hardware factors that influence the performance of each library, and providing insights and recommendations for selecting an appropriate multithreading library for a given application and hardware platform. Ultimately, the study results can help software developers make informed decisions when selecting a multithreading library and optimizing performance for their applications.

ZPP: A Dynamic Technique to Eliminate Cache Pollution in NoC based MPSoCs

Data prefetching efficiently reduces the memory access latency in NUCA architectures as the Last Level Cache (LLC) is shared and distributed across multiple cores. But cache pollution generated by prefetcher reduces its efficiency by causing contention for shared resources such as LLC and the underlying network. The paper proposes Zero Pollution Prefetcher (ZPP) that eliminates cache pollution for NUCA architecture. For this purpose, ZPP uses L1 prefetcher and places the prefetched blocks in the data locations of LLC where modified blocks are stored. Since modified blocks in LLC are stale and request for such blocks are served from the exclusively owned private cache, their space unnecessary consumes power to maintain such stale data in the cache. The benefits of ZPP are (a) Eliminates cache pollution in L1 and LLC by storing prefetched blocks in LLC locations where stale blocks are stored. (b) Insufficient cache space is solved by placing prefetched blocks in LLC as LLCs are larger in size than L1 cache. This helps in prefetching more cache blocks, thereby increasing prefetch aggressiveness. (c) Increasing prefetch aggressiveness increases its coverage. (d) It also maintains an equivalent lookup latency to L1 cache for prefetched blocks. Experimentally it has been found that ZPP increases weighted speedup by 2.19x as compared to a system with no prefetching while prefetch coverage and prefetch accuracy increases by 50%, and 12%, respectively compared to the baseline. 1

Design of a High Performance Vector Processor Based on RISIC-V Architecture

This paper proposes a high performance Vector processor based on the high performance Embedded Core which is named TS800. The TS800 is a 4-core processor based on RISC-V architecture, implements IMAFDV instruction set, supports L2 Cache, branch prediction, sequential pipeline, and dual-issue structure. The traditional CPU mainly supports Scalar calculations, or only supports Vector calculations. For applications such as image and signal processing, there are a large number of data parallel computing operations. To solve the problem of low performance of parallel data calculations in industrial power applications, it is proposed to add VPU hardware implementation in the TS800. The TS800 can support FFT algorithm, adaptive controllers Reinforcement learning and learning-based underlying algorithm requirements. In this paper, the module and data flow between each processing unit and the control circuit, that is, the hardware realization of VPU module are proposed. Large-area units such as float arithmetic, multiplication and division are multiplexed with the Scalar operator in the CPU, while the control circuit is placed in the VPU-ALU, and the area is small. Units such as arithmetic and logic operation instructions, shift operation instructions, comparison operation instructions, and permutation instruction are implemented through the VPU-ALU, which makes the overall design area smaller and the performance better. At the same time, through the fir, fft, conv, matrix, Signal Converge and variance test, it is proved that while executing the same program, the running time of the cpu only with Scalar is 1.44 to 9.55 times that of the CPU with Vector module, which can support the underlying algorithm of the adaptive controller.

Evaluating Fault-Tolerant Techniques on COTS RISC-V NOEL-V Processor in Zynq UltraScale+ FPGA Under Proton Testing

This work evaluates different fault tolerance techniques on the RISC-V NOEL-V processor synthesized into the SRAM-based Zynq UltraScale+ FPGA under proton testing. We investigate the effect of the cache size on the reliability of the processor and the use of scrubbing combined with triplication, duplication with comparison, and cache refreshing. The design area in SRAM-based FPGAs directly affects the soft error cross section. However, results show that increasing the L1 cache size and using the correct combination of mitigation techniques reduces the overall SEE susceptibility of the RISC-V NOEL-V processor.

RISC-V-Based Evaluation and Strategy Exploration of MRAM Triple-Level Hybrid Cache Systems

Magnetic random access memory (MRAM) is considered one of the most promising memories among nonvolatile memories (NVMs), to replace static random access memory (SRAM) in the computing system to improve its cache performance. In this article, performance evaluation and strategy exploration of three-level hybrid cache systems are conducted under the framework of Reduced InstrucTIon Set Computer-Five (RISC-V) instruction set. First, system-level joint calls of Nvsim, Gem5, McPAT, and other cache emulation architectures are implemented based on the system-level simulator called MAGPIE tool. Based on the performance comparison of spin transfer torque (STT)-MRAM, spin-orbit torque (SOT)-MRAM, and SRAM with varied capacities, a variety of combined CPU three-level hybrid cache architectures are simulated. The performances of the proposed hybrid cache systems and the bus impact of interconnecting are evaluated, with better analysis of the cost of CPU system implementation and interactions among levels of cache. The power consumption of different processors with various instruction sets and cores is also evaluated. It is demonstrated that SOT-MRAM and STT-MRAM show great potential applications as L2 and L3 caches in the RISC-V system. RISC-V shows the potential benefits for future CPU cache. Meanwhile, an adaptive stride prefetching strategy is proposed to address the problem of delay hysteresis and high miss rate of STT-MRAM in the L3 cache. The applicability of this strategy to different storage technologies and the comparison with cutting-edge technologies are also illustrated. Simulation results show that the prefetching strategy can achieve at most 64.12% and 94.55% optimization effects on the miss latency and the miss rate of L3 cache, respectively.

Towards an Efficient SIMD Virtual Radio Access Network (vRAN) and Edge Cloud System

Nowadays, virtual Radio Access Network (vRAN) plays a vital role in today's mobile edge system for its better support for latency-sensitive applications. However, our characterization of vRAN on modern processors depicts a frustrating picture of Single-Instruction Multi-Data (SIMD) acceleration. Specifically, the existing data arrangement processes cannot efficiently utilize the ports in modern processors, which leads to high backend bound and fails to saturate the memory bandwidth between registers and the L1 cache. To tackle the issue, we thoroughly examine the state-of-the-art CPU architecture and observe the idle ports which could be utilized by the process. Motivated by this observation, we propose an “Arithmetic Ports Consciousness Mechanism” (APCM) utilizing these idle ports to eliminate the backend bound and saturate the memory bandwidth. The APCM decreases the data arrangement's backend bound from 45 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\%$</tex-math></inline-formula> to 3 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\%$</tex-math></inline-formula> and promotes its memory bandwidth utilization by 4X-16X. Moreover, we illustrate that the APCM can be utilized to promote the performance of typical mobile edge applications such as network routing, image processing, and AI applications. The CPU time of the data arrangement process time of the selected typical mobile edge applications can be reduced by 55 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\%$</tex-math></inline-formula> - 95 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\%$</tex-math></inline-formula> when utilizing the proposed mechanism.

Implementation of a direct-addressing based lattice Boltzmann GPU solver for multiphase flow in porous media

GPU accelerated lattice Boltzmann (LB) simulations of multiphase flow in porous media have become a powerful tool to study fluid displacement process in porous media. For porous structures with a very low porosity, indirect-addressing memory access methods are preferred due to significantly reduction of the memory footprint despite that those methods are more difficult to implement and the resulting performance may be more sensible to the computing architectures, such as cache hierarchy and size. The direct-addressing methods are straightforward to implement and are able to archive high throughput when the porosity is large, while the methods become less efficient when the structures are too sparse. Nevertheless, the direct-addressing methods combined with multi-block grid technique are promising for many applications. In this work, we present a hybrid-way to tackle multiphase flow simulations in porous media, where the direct-addressing method is employed for the main LB evolution while the indirect-addressing method is employed for the complex boundary conditions. The CSF-based LB color-gradient multiphase model and the geometry-based wetting model are employed to increase accuracy and stability. Thanks to the utilization of AA-pattern streaming scheme, non-slip boundary condition of arbitrary orientation can be enforced without extra cost. We perform comprehensive analysis of the computational performance of the present solver on NVIDIA GPUs. For typical sandstones, our results show that the present implementation is able to achieve over 1.5 speedup compared with other direct-addressing schemes on V100 and A100, respectively and, particularly, the computational performance of the boundary kernels is greatly increased thanks to the increased L2 cache size of the latest GPUs.

An Efficient NVM-Based Architecture for Intermittent Computing Under Energy Constraints

Batteryless technology evolved to replace battery technology. Nonvolatile memory (NVM)-based processors were explored to store the program state during a power failure. The energy stored in a capacitor is used for a backup during a power failure. Since the size of a capacitor is fixed and limited, the available energy in a capacitor is also limited and fixed. Thus, the capacitor energy is insufficient to store the entire program state during frequent power failures. This article proposes an architecture that assures safe backup of volatile contents during a power failure under energy constraints. Using a proposed dirty block table (DBT) and writeback queue (WBQ), this work limits the number of dirty blocks in the L1 cache at any given time. We further conducted a set of experiments by varying the parameter sizes to help the user make appropriate design decisions concerning their energy requirements. The proposed architecture decreases energy consumption by 17.56%, the number of writes to NVM by 18.97% at last level cache (LLC), and 10.66% at a main-memory level compared to baseline architecture.

An exa-scale high-performance molecular dynamics simulation program: MODYLAS.

A new version of the highly parallelized general-purpose molecular dynamics (MD) simulation program MODYLAS with high performance on the Fugaku computer was developed. A benchmark test using Fugaku indicated highly efficient communication, single instruction, multiple data (SIMD) processing, and on-cache arithmetic operations. The system's performance deteriorated only slightly, even under high parallelization. In particular, a newly developed minimum transferred data method, requiring a significantly lower amount of data transfer compared to conventional communications, showed significantly high performance. The coordinates and forces of 101 810 176 atoms and the multipole coefficients of the subcells could be distributed to the 32 768 nodes (1 572 864 cores) in 2.3ms during one MD step calculation. The SIMD effective instruction rates for floating-point arithmetic operations in direct force and fast multipole method (FMM) calculations measured on Fugaku were 78.7% and 31.5%, respectively. The development of a data reuse algorithm enhanced the on-cache processing; the cache miss rate for direct force and FMM calculations was only 2.74% and 1.43%, respectively, on the L1 cache and 0.08% and 0.60%, respectively, on the L2 cache. The modified MODYLAS could complete one MD single time-step calculation within 8.5ms for the aforementioned large system. Additionally, the program contains numerous functions for material research that enable free energy calculations, along with the generation of various ensembles and molecular constraints.