Knockout Switch Research Articles

Stochastic model for cell movement in a knockout switch in computer networks

In computer networks, switching is used as a juncture to provide a path to a message to pass on. The knockout switch is a specially designed architecture having equal number of input and output lin...

Fault tolerance in Clos–Knockout multicast ATM switch

AbstractIn this paper, we propose a new architecture for multicast ATM switches with fault tolerant capability based on the Clos–Knockout switch. In the new architecture, each stage has one more redundant switch module. If one switch module is faulty, the redundant module would replace the faulty one. On the other hand, under the fault‐free condition, the redundant modules in the second and third stages will provide additional alternative internal paths, and hence improve the performance. The performance analysis shows that the cell loss probability is lower than the original architecture when all modules are fault free, and the reliability of the original architecture is improved. Copyright © 2002 John Wiley & Sons, Ltd.

Performance analysis of knockout ATM switch with batcher network for multiple priority classes

AbstractRecently, there has been a need for a network architecture with a variety of traffic. In order to meet the requirements, a conventional knockout switch for two priority classes has been proposed and evaluated by numerical calculations. However, the switch is analyzed for multiple priority classes even though there are many kinds of traffic in the network. In this paper, a knockout packet switch with a batcher network for multiple classes is proposed in order to satisfy different requirements for loss probability of packets with multiple classes. The proposed model involves sorting packets according to the small identification number of a priority class by a batcher network. Hence, it is possible to handle packets with multiple classes. The proposed switch consists of N modules structured with filters, batcher network, and output buffers. As a result, we show that the proposed model is useful in satisfying different requirements for packet loss probability with multiple classes. © 2001 Scripta Technica, Electron Comm Jpn Pt 2, 84(7): 10–18, 2001

WDM knockout switch with multi-output-port wavelength-channel selectors

This paper proposes the photonic knockout switch that uses wavelength division multiplexing (WDM). The proposed switch uses two types of WDM switching: broadcast-and-select (B and S) switching and wavelength routing. To extend the size of the knockout switch concentrator, a multi-output-port wavelength-channel selector is used, which enables us to reduce the number of optical gates and wavelength routers. Simple and distributed contention control becomes possible in the optical domain through the use of the wavelength-routing switch. In this switch, coherent crosstalk is a serious problem. We measured the bit error rates of a four-output-port wavelength-channel selector. The power penalty due to the presence of coherent crosstalk is less than 1 dB.

Performance Analysis of the Knockout Switch Under Bursty Traffic Based on a Stochastic Activity Network Model

The possibility of Asynchronous Transfer Mode (ATM)-based B-ISDNs has made desirable the integration of diverse services like voice, data, and multimedia. The success of these high-speed networks is critically dependent on the availability of Fast Packet Switches (FPS) with the capacity to switch and route at high speeds and to provide the required Quality of Service (QoS). The diversity of the applications, however, leads to widely differing QoS demands. The knockout switch is an FPS with low cell-loss probability and latency under steady input traffic. In this paper, we analyze the performance of the knockout switch in terms of cell loss probabil ities and distribution of queue length for a wide range of burst parameters. The switch is modeled using Stochastic Activity Networks (SANs), and the underlying Markov processes are generated and solved using UltraSAN. The results provide useful information about the switch sensitivity and robustness under a variety of burst parameters and illustrate the appropriateness of SANs for modeling and analyzing telecommunication switch architectures.

Design of knockout concentrators

The knockout switch architecture has been found attractive for large-scale switch implementations because of its satisfactory cell loss performance, with constant output buffer speed-up independent of switch dimension. The per port hardware complexity of a knockout concentrator, however, does grow linearly with the switch dimension. In the paper, several approaches are investigated to reduce the hardware complexity of the knockout concentrator while retaining the cell loss performance. A bufferless hierarchical concentrator architecture with reduced hardware complexity is derived. The concentrator complexity can be further reduced by introducing buffers in the concentrator, and the trade-off is analysed. Furthermore, output grouping may be applied in the buffered hierarchical concentrator to reduce the per port complexity. Two large-scale switch design examples are derived using the proposed design approaches, producing a complexity reduction ranging from 1.2% to 89.7%.

Fault diagnosis of a distributed knockout switch

The distributed knockout switch has multiple paths between any input and output pair and thus is inherently robust to faults without the need of adding any additional switch elements. However, to achieve fault tolerance, one has to first detect and locate the faults. The authors present an efficient fault diagnosis procedure to detect, locate, and identify the fault type of single switch element faults for the switch element array of the distributed knockout switch. To facilitate fault diagnosis, the operation of switch elements is slightly modified. The diagnosis procedure can locate most single switch element faults in two phases. Faults which cannot be located in two phases can always be located in a third phase. Binary search algorithms are developed to locate some kinds of single switch element faults in the third phase.

ATM switch with multimedia traffic priority control

AbstractIn this paper, a novel ATM switch with a dynamic multimedia traffic priority control scheme (HQMS: Hybrid combination of Queue Length Threshold and Minimum Laxity Threshold Scheme) is proposed. The ATM switch has the same basic topology as the Knockout switch, but employs a simpler N×L concentration scheme, which takes into account cells belonging to different priority levels. The structure of the switch supports two priority mechanisms. The first one is called priority discarding and acts as a local congestion control scheme within the switch fabric satisfying different cell loss requirements of different ATM traffic classes. The second one is called priority scheduling and uses two priority methods: a space priority method used for the control of the buffer space when an overflow condition occurs andor when the expiration of the maximum admissible delay of the delay sensitive cells takes place and the service priority method which assigns transmission priorities to the buffered cells. A hardware implementation of the two priority mechanisms of the HQMS is presented. The performance of the switch has been studied by simulation, considering three ATM classes (video, data, voice) with different source models. The results have shown that for a large range of traffic load, the proposed HQMS satisfies the loss and delay requirements of the three classes.

Design and performance evaluation of a distributed knockout switch with input and output buffers

A nonblocking ATM switch with input and output buffers is proposed and its performance is evaluated. The proposed switch is a modified version of an existing distributed-knockout-switch . In the proposed switch architecture, an input port with a nonempty queue always sends a cell to the switch at the beginning of each time slot. The cell sent out from an input port reaches either its destination output port (if it wins the contention) or a different input port (if it loses). A priority scheme is adopted to preserve service-cell sequencing. A cell is discarded if it loses a predetermined number of consecutive contentions. A modified architecture which can provide multicast service is also presented. Simulations are performed to evaluate the proposed switch architecture under both uniform- and hot-spot nonuniform-traffic models.

The knockout switch under nonuniform traffic

The knockout switch is a nonblocking, high-performance switch suitable for broadband packet switching. It allows packet losses, but the probability of a packet loss can be kept extremely small in a cost-effective way. The performance of the knockout switch was analyzed under uniform traffic. In this paper, we present a new, more general analytic model of the knockout switch, which enables us to evaluate the knockout switch under nonuniform traffic. The new model also incorporates the effects of a concentrator and a shared buffer on the packet loss probability. Numerical results for nonuniform traffic patterns of interest are presented. >

KSMINs: knockout switch-based multistage interconnection networks for high-speed packet switching

We propose knockout switch-based multistage interconnection networks (KSMINs) for fast packet switching, combining the well-known knockout switch and the concept of multistage interconnection networks. The main objective is to reduce the severe pin requirements of large knockout switches through a phased address filtering. We present an approximate Markov-chain model of KSMINs to study the performance of KSMINs with different numbers of address-filtering phases. The model is shown to be accurate within 5% for all the cases considered and within 20% for the meaningful cases of the buffer sizes /spl ges/4. For the (256/spl times/256) KSMIN, two-phase address filtering based on the (16/spl times/16) knockout switches is shown to perform very closely to the single-stage knockout switch for a reduced hardware cost.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Cell loss analysis of two-class priority generalisedknockout switch

To support integrated services, an ATM switch must be capable of handling the requirements of different services. In this Letter we introduce a two-class priority scheme to the knockout switch (KS) and the generalised knockout switch (GKS). The priority switches achieve a much lower loss rate of high-priority cells than no-priority switches. Using the priority scheme in the GKS is more efficient than in the KS to reduce the interconnect complexity of the switch.

Performance analysis of the knockout switch with input buffers

Since the asynchronous transfer mode (ATM) has been strongly promoted as the transport structure for broadband integrated services digital networks, a variety of ATM switching architectures have been proposed. The knockout switch, which is one of the well known ATM switches, has a single-stage architecture and adopts an output buffering method. It has excellent traffic performance (cell loss probability, maximum throughput and delay, etc.), but needs many switch elements and buffers. The authors propose an ATM switch, called a knockout switch with input buffers. The proposed switch has almost the same traffic performance as the existing knockout switch but needs fewer switch elements and buffers than the existing knockout switch. The authors analyse the traffic performance and complexity (i.e. the number of switch elements and buffers required) of the proposed architecture by discrete-time Markov chain models and compare them with those of the existing knockout switch. It is found that the proposed architecture could reduce the need for over 40% of the switch elements and over 30% of the buffers while satisfying the given loss requirements.

Design and performance analysis of input-output buffering delta-based ATM switch with backpressure mechanism

A new delta-based ATM switch architecture is described that is based on expanding a delta network so that blocking is eased while preserving self routing and path uniqueness. The switch employs a combined external input-output buffering strategy, but operates-in such a way that output buffer overflows never happen. An analytical model, that takes into account this backpressure mechanism, is developed for arbitrary switch parameters, and computer simulations are used to assess the accuracy of the analysis. It is shown that a maximum throughput of above 0.90 can be achieved for a large-size switch using an expansion factor of 16. It is also shown that the backpressure mechanism can reduce the overall memory size needed to achieve a given cell loss performance, compared with the case where it is not used. The switch is shown to compare very well to-the-well-known knockout switch in terms of both performance and complexity. Finally, a distinctive feature of the proposed architecture is that internal node buffering can be used without disturbing cell sequencing.

The Christmas-tree switch: an output queuing space-division fast packet switch based on interleaving distribution and concentration functions

Abstract Some space-division fast packet switch architectures avoid blocking completely by providing N2 disjoint paths from N inputs to N outputs. Two prominent examples of such architectures are the Bus-Matrix switch and the Knockout switch. In this paper, we propose a self-routing space-division fast packet switch architecture which achieves output queuing with a reduced number of internal paths (O(N)). The switch architecture is a multi-level binary tree in which each branch constitutes a group of paths that are shared by all the packets destined to a subset of output ports. The reduction in the number of internal paths is obtained by performing packet distribution and packet concentration functions at each level of the tree. Packet loss may occur at each level of the tree and is dependent on the degree of concentration exercised at that level. Owing to the binary tree structure of the switching fabric, a simple mathematical analysis is performed in order to determine the concentration parameters appropriate for each level to meet a given overall packet loss rate. Several implementation architectures based on sorting networks are described.

Sorcon switch: a new cell switching architecture

An ATM switch is proposed which belongs to the class of fabrics with N2 disjoint paths. It has the same topology as the knockout switch, but employs a novel modular concentration scheme with simpler structure and substantially lower delay.

HiMA: a hierarchical and modular ATM switch with partially shared output buffer

The authors propose a hierarchical and modular ATM switch. To improve the queueing performance, they adopt the output queueing technique and allow several outputs to partially share the same output buffer space. The performance of the proposed switch is evaluated under uniform and nonuniform traffic patterns. Comparisons with the knockout switch, recursive switch, SCOQ, and Christmas-tree switch show that, in terms of complexity, crosspoint count, scalability and synchronisation, the proposed switch is superior.

Performance analysis of nonblocking packet switch with input and output buffers

The performance of nonblocking packet switches such as the knockout switch and Batcher banyan switch for high-speed communication networks can be improved as the switching capacity L per output increases; the switching capacity per output refers to the maximum number of packets transferred to an output during a slot. The N*N switch with L=N was shown to attain the best possible performance by M.J. Karol et al. (1987). Here a N*N nonblocking packet switch with input and output buffers is analyzed for an arbitrary number of L such that 1 >

Rearrangeable switch fabric for fast packet switching

The knockout switch is a switch fabric proposed for fast packet switching. Under certain non-uniform traffic patterns (i.e. a ‘hot spot contention’) the switch exhibits an increase in the packet loss rate. A rearrangeable switch fabric based on knockout switch concepts is proposed which, on the occurrence of ‘hot spot’ traffic, reconfigures itself to guarantee a very low packet loss rate. The new switch architecture is presented, and parameters affecting performance are analysed. An implementation based on dynamically reconfigurable VLSI components is proposed.

A recursive modular terabit/second ATM switch

The author proposes a recursive modular architecture for a very large scale asynchronous transfer mode (ATM) switch. By extending the concept of the original knockout switch, the cell filtering and contention resolution functions are distributed over many small switch elements, which are arranged in a crossbar structure. The output ports of a switch fabric are partitioned into a number of groups by a novel grouping network to permit sharing of the routing paths in the same group. This partitioning and sharing concept is applied recursively to construct the entire switch elements. The technique of channel grouping for trunk circuits can be incorporated in the proposed ATM switch to improve the cell loss/delay performance while the cells' sequences are retained. A prototype circuit for the key switch element has been designed, and it has been shown that more than 4000 of the switch elements can be integrated into a VLSI chip with existing CMOS 1- mu m technology.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>