Design of knockout concentrators

Abstract

The knockout switch architecture has been found attractive for large-scale switch implementations because of its satisfactory cell loss performance, with constant output buffer speed-up independent of switch dimension. The per port hardware complexity of a knockout concentrator, however, does grow linearly with the switch dimension. In the paper, several approaches are investigated to reduce the hardware complexity of the knockout concentrator while retaining the cell loss performance. A bufferless hierarchical concentrator architecture with reduced hardware complexity is derived. The concentrator complexity can be further reduced by introducing buffers in the concentrator, and the trade-off is analysed. Furthermore, output grouping may be applied in the buffered hierarchical concentrator to reduce the per port complexity. Two large-scale switch design examples are derived using the proposed design approaches, producing a complexity reduction ranging from 1.2% to 89.7%.