Design Kit Research Articles

A Review on the Long-Term Performance of Proton Exchange Membrane Fuel Cells: From Degradation Modeling to the Effects of Bipolar Plates, Sealings, and Contaminants

Proton-exchange membrane fuel cells (PEMFCs) are regarded as promising alternatives to internal combustion engines (ICEs) to reduce pollution. Recent research on PEMFCs focuses on achieving higher power densities, reducing the refueling time, mitigating the final price, and decreasing the degradations, to facilitate the commercialization of hydrogen mobility. The design of bipolar plates and compression kits, in addition to their coating, can effectively improve performance, increase durability, and support water/thermal management. Past reviews usually focused on the specific aspect, which can hardly provide readers with a complete picture of the key challenges facing and advances in the long-term performance of PEMFCs. This paper aims to deliver a comprehensive source to review, from both experimental, analytical and numerical viewpoints, design challenges, degradation modeling, protective coatings for bipolar plates, and key operational challenges facing and solutions to the stack to prevent contamination. The significant research gaps in the long-term performance of PEMFCs are identified as (1) improved bipolar-plate design and coating, (2) the optimization of the design of sealing and compression kits to reduce mechanical stresses, and (3) stack degradation regarding fuel contamination and dynamic operation.

In-Memory Hamming Error-Correcting Code in Memristor Crossbar

This article proposes an in-memory Hamming error-correcting code (ECC) in the memristor crossbar array (CBA). Based on the unique <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}{-}{V}$ </tex-math></inline-formula> characteristic of complementary resistive switching (CRS) memristor, this work discovers that a combination of three memristors behaves as a stateful EXCLUSIVE-OR (XOR) logic device. In addition, a two-step (build-up and fire) current-mode CBA driving scheme is proposed to realize a linear increment of the build-up voltage that is proportional to the number of low-resistance state (LRS) memristors in the array. Combining the proposed XOR logic device and the driving scheme, we realize a complete stateful XOR logic, which enables a fully functional in-memory Hamming ECC, including parity bit generation and storage followed by syndrome vector calculation/readout. The proposed technique is verified by a simulation program with integrated circuit emphasis (SPICE) simulations, with a Verilog-A CRS memristor model and a commercial 45-nm CMOS process design kit (PDK). The verification results prove that the proposed in-memory ECC perfectly detects error regardless of data patterns and error locations with enough margin.

DESIGN FOR EMOTIONAL DURABILITY: THE CASE OF HOUSEHOLD LIGHT DESIGN

Designers’ hands-on experience in research through design process contributes them to produce&#x0D; and share knowledge from their own design practices. In this study, the primary purpose was exploring&#x0D; sustainable design concepts and developing solutions for improving the product lifespan of household light&#x0D; with research through design process. With a particular focus on “emotionally durable design”, “product&#x0D; personalisation”, and “localisation” were considered fruitful concepts. The do-it-yourself (DIY) approach,&#x0D; which means that users participate in production, and the halfway product rationale, which leaves space for&#x0D; users to complete the production, were the concepts used in personalisation. The outcome of the research&#x0D; through design process was a wall lamp manufactured with different scales of production, involving&#x0D; personalisation features facilitated by DIY and halfway product rationale. For “localisation”, different scales of&#x0D; production opportunities were explored, and a design kit as a halfway product was considered as a sustainable&#x0D; design solution. DIY approach was benefited for producing complementary lace lampshade. In the design&#x0D; for sustainability framework, it is seen that experimenting and engaging with locally available materials and&#x0D; manufacturing capabilities in the research through design process nurtured developing sustainable design&#x0D; solutions.

Low Power Squaring Circuit Using Single Voltage Differencing Buffered Amplifier

In this paper, a squaring circuit is proposed using a voltage differencing buffered amplifier (VDBA). The squaring circuit consists of a VDBA, two NMOS transistors and one resistor. The proposed structure facilitates easy cascading without any requirement of additional buffer. The behavior of the proposed structure is analyzed in the presence of nonidealities of VDBA and the corresponding mathematical formulations are also presented. The workability of the proposed circuit is verified through Cadence Virtuoso Analog Design Environment tool using 0.18[Formula: see text][Formula: see text]m generic process design kit parameters. Both pre- and post-layout simulation results have been included to confirm the functionality of the proposed circuit. The 3-dB frequency of the proposed circuit using schematic and post-layout-driven simulations is observed to be 3.77 and 3.72[Formula: see text]MHz, respectively. The power consumption of the proposed squaring circuit is found to be 110[Formula: see text][Formula: see text]W. The process, voltage and temperature (PVT) analysis has also been carried out to check the robustness of the proposed circuit. Total harmonic distortion for the entire input range is found to be less than 3%.

ASAP5: A predictive PDK for the 5 nm node

We present a predictive process design kit (PDK) for the 5 nm technology node, the ASAP5 PDK. ASAP5 is not related to a particular foundry and the assumptions are derived from literature. It incorporates several innovations that the semiconductor industry has adopted to address scaling challenges, improve reliability and performance. These include contact over active gate (COG), fully self-aligned vias (FSAVs), single diffusion breaks (SDBs), and cobalt interconnects. We discuss implications of these changes in the context of standard cell and static random access (SRAM) bit cells. Interconnect modelling is improved and incorporates the effects of metal fill and barrier geometry on line resistivity. Different metal fill and barrier configurations are compared to determine the PDK interconnect stack. We discuss design rule assumptions for the key layers. The PDK uses horizontal nanowire field-effect transistors (NWFETs) for better ON and OFF-state performance. The transistor compact models are calibrated to the 3-D technology computer-aided design (TCAD) simulation results.

A Methodology to Design Static NCL Libraries

The Null Convention Logic (NCL) based asynchronous design technique has interested researchers because this technique had overcome disadvantages of the synchronous technique, such as noise, glitches, clock skew and power. However, using the NCL-based asynchronous design method is difficult for university students and researchers because of the lack of standard NCL cell libraries. Therefore, in this paper, a novel flow is proposed to design NCL cell libraries. These libraries are used to synthesize NCL-based asynchronous designs. We chose the static NCL cell library to illustrate the proposed design solution because this library is one of the most basic NCL libraries. Static NCL cells in this library are designed based on the Process Design Kit 45nm technology and are implemented by the Virtuoso and the Design Compiler (DC) tool. In addition, the Ocean script and Electronic Design Automation (EDA) environment are used for supporting designs and simulations. A complete library of 27 NCL cells was designed to serve for study and research. We also implemented synthesis for NCL full adders using this library and compared our synthesis results with the results of other authors. The comparison results indicated that our results were a 20% improvement on power consumption.

Subscale HTS Fusion Conductor Fabrication and Testing in High Magnetic Background Field

In actual or future fusion machines like ITER, JT-60SA, W7-X or the present EU-DEMO design, low temperature superconductor (LTS) cables are used or planned to be used in the magnet system to create the strong magnetic field necessary for plasma confinement. High temperature superconductors (HTS) offer the potential to increase the magnetic field strength in fusion magnet systems even further, allowing to build more compact fusion machines or to realize higher flux swings in central solenoids. In this work, two HTS conductors were fabricated and characterized by high current testing at 77 K in self-field conditions and at 4.2 K with an external magnetic field up to 12 T. Both samples offer the same amount of superconducting HTS tapes but differ in the assembly process and termination type. These tests were intended to validate the current KIT design of a HTS CroCo triplet conductor and to qualify a low degradation cable manufacturing process.

A computer‐aided design tool for RF filters design automation

SummaryIn this paper, we propose a computer‐aided design (CAD) tool in the electronic design automation (EDA) domain. This tool is dedicated for the design and simulation of Radiofrequency (RF) filters that are integrated into Advanced Design System (ADS) software. It includes a graphical user interface (GUI) developed using the design kit feature available under ADS and “Application Extension Language (AEL)” as a programming language. This will extend the existing smart filter design tool under ADS by adding more types of RF filters. The proposed feature will provide to users a rapid and an accurate tool to design and simulate RF filters by presenting interactive menus facilitating the process. As a proof of concept, an application of this tool is presented for the design of a Dual‐Behavior Resonators filter. The tool can be upgraded by adding other RF components and even entire front‐end circuits. In a future step, this tool will be enhanced by adding tuning capabilities to RF filters using ideal capacitors and varactors, which will make it the first one of its kind in the literature.

Preliminary Evidence-Based Method of Medical Kit Design for Wilderness Expeditions Modeled by a High-Altitude Expedition to Mount Kilimanjaro

BackgroundWilderness expeditions require extensive planning and the correct medical supplies to ensure clinical care is possible in the event of illness or injury. There are gaps in the literature regarding evidence-based methods for medical kit design. ObjectivesThis report describes a preliminary method for predicting medical events to determine medical supply requirements for a wilderness expedition. The performance of this method was evaluated using data from the 2017 Equal Playing Field (EPF) expedition to Mount Kilimanjaro. MethodsEight reports documenting medical events during wilderness expeditions were reviewed. Incidence data were consolidated into a new dataset, and a subset of data from adventure race expeditions (ARS) was created. The cumulative incidence of medical events was then predicted for the 9-day EPF expedition. The medical supply list was determined based on indication. The effectiveness of the full dataset and ARS to predict the cumulative incidence of medical events by category during the EPF expedition was evaluated using regression analysis. ResultsThe ARS predicted a higher incidence rate of medical events than the full dataset did but underestimated the EPF expedition incidence rate. The full dataset was a weak predictor of the cumulative incidence of medical events by category during the EPF expedition, while the ARS was a strong predictor. The finalized medical kit overestimated all nonreusable supplies. ConclusionsThe medical kit created using this method managed all medical events in the field. This report demonstrates the potential utility of using a tailored, evidence-based approach to design a medical kit for wilderness expeditions.

Metrology for low-cost CO&amp;lt;sub&amp;gt;2&amp;lt;/sub&amp;gt; sensors applications: the case of a steady-state through-flow (SS-TF) chamber for CO&amp;lt;sub&amp;gt;2&amp;lt;/sub&amp;gt; fluxes observations

Abstract. Soil CO2 emissions are one of the largest contributions to the global carbon cycle, and a full understanding of processes generating them and how climate change may modify them is needed and still uncertain. Thus, a dense spatial and temporal network of CO2 flux measurements from soil could help reduce uncertainty in the global carbon budgets. In the present study, the design, assembly, and calibration of low-cost air enquirer kits, including CO2 and environmental parameters sensors, is presented. Different types of calibrations for the CO2 sensors and their associated errors are calculated. In addition, for the first time, this type of sensor has been applied to design, develop, and test a new steady-state through-flow (SS-TF) chamber for simultaneous measurements of CO2 fluxes in soil and CO2 concentrations in air. The sensors' responses were corrected for temperature, relative humidity, and pressure conditions in order to reduce the uncertainty in the measured CO2 values and of the following calculated CO2 fluxes based on SS-TF. CO2 soil fluxes measured by the proposed SS-TF and by a standard closed non-steady-state non-through-flow (NSS-NTF) chamber were briefly compared to ensure the reliability of the results. The use of a multiparametric fitting reduced the total uncertainty of the CO2 concentration measurements by 62 %, compared with the uncertainty that occurred when a simple CO2 calibration was applied, and by 90 %, when compared to the uncertainty declared by the manufacturer. The new SS-TF system allows the continuous measurement of CO2 fluxes and CO2 ambient air with low cost (EUR ∼1200), low energy demand (&lt;5 W), and low maintenance (twice per year due to sensor calibration requirements).

Adjusting thermal stability in double-barrier MTJ for energy improvement in cryogenic STT-MRAMs

This paper investigates the impact of thermal stability relaxation in double-barrier magnetic tunnel junctions (DMTJs) for energy-efficient spin-transfer torque magnetic random access memories (STT-MRAMs) operating at the liquid nitrogen boiling point (77 K). Our study is carried out through a macrospin-based Verilog-A compact model of DMTJ, along with a 65 nm commercial process design kit (PDK) calibrated down to 77 K under silicon measurements. Comprehensive bitcell-level electrical characterization is used to estimate the energy/latency per operation and leakage power at the memory architecture-level. As a main result of our analysis, we show that energy-efficient small-to-large embedded memories can be obtained by significantly relaxing the non-volatility requirement of DMTJ devices at room temperature (i.e., by reducing the cross-section area), while maintaining the typical 10-years retention time at cryogenic temperatures. This makes DMTJ-based STT-MRAM operating at 77 K more energy-efficient than six-transistors static random-access memory (6T-SRAM) under both read and write accesses (−56% and −37% on average, respectively). Obtained results thus prove that DMTJ-based STT-MRAM with relaxed retention time is a promising alternative for the realization of reliable and energy-efficient embedded memories operating at cryogenic temperatures.

Breakout EDU

Breakout EDU

PIXAPP Photonics Packaging Pilot Line – Development of a Silicon Photonic Optical Transceiver With Pluggable Fiber Connectivity

This paper demonstrates how the PIXAPP Photonics Packaging Pilot Line uses its extensive packaging capabilities across its European partner network to design and assemble a highly integrated silicon photonic-based optical transceiver. The processes used are based on PIXAPP&#x0027;s open access packaging design rules or Assembly Design Kit (ADK). The transceiver was designed to have the Tx and Rx elements integrated on to a single silicon photonic chip, together with flipchip control electronics, hybrid laser and micro-optics. The transceiver used the on-chip micro-optics to enable a pluggable fiber connection, avoiding the need to bond optical fibers directly to the photonic chip. Finally, the packaged transceiver module was tested, showing 56 Gb&#x002F;s loop-back modulation and de-modulation, validating both the transmitter and receiver performance.

Prediction Methodology for Next-generation Device Characteristics using Machine Learning

In this article, we propose a prediction methodology for next-generation device characteristics for process design kit (PDK) models that utilize various machine learning algorithms to achieve high accuracy and reduction of development turn-around time (TAT). The Berkeley short-channel IGFET model (BSIM) is used for generating datasets, while n-channel MOSFET compact model is used for peripheral circuits in dynamic random-access memory (DRAM) technology. Datasets for training comprise device characteristics that use compact models in present-generation products. In addition, a compact model of next-generation products is used for validating datasets. We demonstrate that our prediction methodology using random forest regression provides high accuracy of less than 0.7% RMSE and reduces development TAT.

A Novel Energy Efficient and Process Immune Schmitt Trigger Circuit Design Using FinFET Technology

Continuous scaling of MOS (Metal oxide semiconductor) devices gives rise to drastic increase in leakage power dissipation, which overall increases the total power dissipation. This happens due to increase in short channel effects. FinFET device has the capability to reduce short channel effects, hence reduces power dissipation as well. In this paper short-gate FinFET (fin type field effect transistor) based Schmitt trigger using LCNT (Leakage Control NMOS transistor) technique is proposed using ASAP7 PDK (A 7nm FinFET Predictive process design kit) at 7nm technology node and comparative analysis is provided with the one without LCNT technique. The simulated results shows that FinFET based Schmitt trigger using LCNT technique reduces average power dissipation and power delay product (PDP) by 36.97% and 35.6%, respectively compared to one without FinFET LCNT technique. The reliability analysis using Monte Carlo approach at ±10% process, voltage and temperature (PVT) variation under 3σ Gaussian distribution shows that LCNT FinFET Schmitt trigger provides better performance compared to FinFET Schmitt trigger at 7nm technology node.

An Investigation of HZO-Based n/p-FeFET Operation Mechanism and Improved Device Performance by the Electron Detrapping Mode

Ferroelectric field-effect transistor (FeFET) is a promising nonvolatile memory device because of its CMOS compatibility, scalability, and energy efficiency. However, the device physics has not been studied well, which hinders FeFET development and process design kit (PDK) construction. In this article, we report a comprehensive understanding of the n/p-FeFET operation mechanism as a nonvolatile memory device, for the first time, based on quasi-static split <i>CV</i> measurement. We also suggest a new methodology to examine the device and show the existence of excess trapped charge and the true nonvolatile polarization. Furthermore, we found that charge trapping is necessary to switch polarization in FeFET. Finally, based on our physical findings and insights, we propose a new erase mode that leads to a wider memory window and higher write endurance (&#x003E; 10¹⁰ cycles), even without optimizing the device fabrication process.

Solution for Model Parameter Optimization and Prediction of Next-Generation Device DC Characteristics

We present a novel method to predict the next-generation device characteristics and model optimization solutions for the process design kit. We demonstrate the next-generation prediction methodology from the creation of device characteristics to the development of a compact model. The proposed method achieves high accuracy and reduction in development turnaround time.

Analysis and Modeling of an 11.8 GHz Fin Resonant Body Transistor in a 14 nm FinFET CMOS Process.

In this work, a compact model is presented for a 14-nm CMOS-based fin resonant body transistor (fRBT) operating at a frequency of 11.8 GHz and targeting radio frequency (RF) generation/filtering for next-generation radio communication, clocking, and sensing applications. Analysis of the phononic dispersion characteristics of the device, which informs the model development, shows the presence of displacement component coupling due to the periodic nature of the back-end-of-line (BEOL) metal phononic crystal (PnC). An eigenfrequency-based extraction process, applicable to resonators based on electrostatic force transduction, has been used to model the resonance cavity. Augmented forms of the Berkeley short channel IGFET model (BSIM)-common multigate (CMG) model for FinFETs are used to model the drive and sense transistors in the fRBT. This model framework allows easy integration with the foundry-supplied process design kits (PDKs) and circuit simulators while being flexible toward change in transduction mechanisms and device architecture. Ultimately, the behavior is validated against RF measured data for the fabricated fRBT device under different operating conditions, leading to the demonstration of the first complete model for this class of resonant device integrated seamlessly in the CMOS stack.

Different combinations of monoclonal antibodies and polyclonal antibodies in the design of neonatal hypothyroidism diagnostic kit

Neonatal hypothyroidism is a deficiency of thyroid hormones at birth that can cause lifelong mental and physical disorders in humans. Lack of timely detection could lead to irreversible damage by neonatal hypothyroidism. However, it could be managed quickly and efficiently via timely diagnosis. The screening programs rely on immunoassays to diagnose neonatal hypothyroidism in most countries. This method is time-consuming, needs laboratory equipment, and should be performed by trained and skilled technicians. Given these circumstances, the ELISA method is not a preferable method for the diagnosing of neonatal hypothyroidism. However, it can be used as a confirmatory method in infants with suspected and unknown neonatal hypothyroidism. In the present study, the homemade SR95-1, SR95-2, and SR95-3 anti-β-TSH polyclonal and the commercially available monoclonal antibodies were used to detect β-TSH in a rapid assay kit design hypothyroidism screening. To design the kit, the different combinations of the antibodies were used to establish a sandwich immune-chromatography method. The designed rapid neonatal hypothyroidism tests were used to measure neonatal β-TSH in 100 dry blood samples. This study showed that the best antibody pair in terms of sensitivity is the SR95-1 antibody as capture antibody and the SR95-2 as a conjugated antibody. Using 100 clinical samples, the designed assay was shown to have 94% sensitivity, 83% specificity, and 94% accuracy. The results showed that polyclonal antibodies (SR95-1 as capture) and SR95-2 (as detector) antibodies can detect the reference range of β-TSH in dried blood samples and can be used in the screening of neonatal hypothyroidism.

A Novel STT–SOT MTJ-Based Nonvolatile SRAM for Power Gating Applications

This article proposes novel nonvolatile (NV) static random access memory (SRAM) circuits based on spin transfer torque (STT) and spin orbit torque (SOT) operated magnetic tunnel junction (MTJ) device for energy-efficient power gating circuits. In which, two different designs of 9T-2MTJs and 10T-2MTJ-based NV SRAM circuits are proposed for low power, high noise margin, and faster switching speed with less area overhead. The proposed architecture uses a smaller number of transistor combinations to accommodate low-power operation with compact cell size when compared with available pieces of literature. Also, the combination of nMOS and pMOS transistors in the proposed architecture enhances the driving capability of the circuit for both low and high input operations. Here, the electrical characteristics of the proposed designs have been compared and contrasted with the available 11T-2MTJ and 7T-2D-2MTJ non volatile static random access memory (NVSRAM) and 6T SRAM circuits using a UMC-40 nm design kit and physics-based STT–SOT MTJ Verilog-A Model. The proposed 9T-2MTJ-based NVSRAM was found to be a better alternative and offers improved performance in terms of higher restore noise margin and lower power consumption than other circuits reported at this node. Moreover, the studied 10T-2MTJ exhibits an improved write and hold noise margin than the proposed/available 9T/7T-2D/11T-2MTJ circuits.