Kerf Loss Research Articles

Challenge to EDM Slicing of Single Crystal SiC with Blade Electrode Utilizing a Reciprocating Worktable

Single crystal silicon carbide is a promising material for producing next-generation power electronic devices owing to its outstanding physical properties of wide band gap, high dielectric strength, high heat resistance and high electron saturation drift velocity etc. However, slicing of SiC wafer is very time and cost consuming with conventional abrasive multi-wire saw method due to the extremely high hardness of SiC, especially when the diameter of SiC ingot becomes larger. In recent years wire EDM slicing method is being developed as an alternative method for wafering SiC ingots. However, wire vibration and wire breakage problems are inevitable in the process. Wire vibration causes a low cutting accuracy and wire breakage results in a low cutting efficiency. In this study, aiming to solve these problems and improve the EDM slicing performances of SiC, a new EDM wafering method which utilizes a blade electrode is proposed. The slicing process was realized by applying a relative motion between a tensioned blade tool electrode and a workpiece making use of a reciprocating worktable. The development of the experimental setup and the machining experiments are described in detail in this paper. The tool wear ratio, slicing speed, and kerf loss were investigated through slicing experiments and the characteristics of this new method are discussed.

Kerf loss silicon as a cost-effective, high-efficiency, and convenient energy carrier: additive-mediated rapid hydrogen production and integrated systems for electricity generation and hydrogen storage

Kerf loss silicon was used for additive-mediated rapid hydrogen production with a rate of 4.72 × 10−3g(H2) per s per g(Si) and a yield of 92%. A silicon-based integrated system for electricity generation and hydrogen storage was demonstrated.

Novel RGS materials with high fill factors and no material-induced shunts with record solar cell efficiencies exceeding 16%

Kerf losses due to ingot and wafer sawing can be avoided by solidifying the silicon wafers directly from the melt by the Ribbon Growth on Substrate (RGS) process, thus significantly reducing the wafer cost. However, up to now solar cells made from standard RGS material suffered from shunting problems due to current collecting structures. This resulted in lower fill factor values and hence in lower efficiencies compared to solar cells made from block-cast multicrystalline silicon (mc-Si) materials. In this contribution two novel RGS materials are presented and investigated. Solar cells processed from these new materials have fill factor values above 78%, comparable to those of mc-Si. The increased fill factor values can be explained by the absence of current collecting structures as concluded from a comparative analysis of spatially resolved Light Beam Induced Current (LBIC) measurements and Electroluminescence (EL) images, and from infrared transmission microscopy investigations. Additionally the improved material quality resulted in open-circuit voltage VOC values up to 608mV. This enhanced material quality, in combination with increased fill factor values, resulted in record efficiencies above 16% (certified by Fraunhofer ISE CalLab). This represents a significant improvement compared to the former efficiency record of 14.4% for standard RGS material.

Fundamental Micro-Grooving Characteristics of Hard and Brittle Materials with a Fine Wire Tool

Thinning of the silicon wafers and decrease in kerf loss can minimize the production costs of semiconductor products. Currently, the quantity of kerf loss is about the same as the volume of the wafer itself. If we drastically reduce kerf loss, we can easily lower production costs. Therefore, we studied techniques for slicing silicon wafers with reduced kerf loss using a wire tool. As a first step, we performed micro-grooving with a fine wire tool. In this paper, we discuss the micro-grooving performance of a fine wire tool made of tungsten. A borosilicate glass is used as the work material. The main conclusions are as follows: When a fine wire tool and small-diameter abrasives are used, the kerf loss decreases. However, the strength of fine wire tools is very low. The relative velocity and abrasive diameters have a significant influence on the micro-grooving characteristics. Fine wire tools are easily fractured at fast relative velocities and with large-diameter abrasives. However, the grooving rate increases. Groove depth and grooving efficiency do not depend on the relative velocity and are dependent on the abrasive diameter.

Investigation on diamond wire break-in and its effects on cutting performance in multi-wire sawing

Multi-wire sawing with diamond wire is used to slice hard and brittle materials such as sapphire, silicon carbide, or silicon into thin wafers. Compared to traditional slicing methods, multi-wire sawing with diamond wire has many advantages, including reduced kerf loss, efficient machining, and improved form accuracy. However, the process is associated with several unexpected problems, including considerable kerf loss and inefficient cutting during the initial cutting step. Thus, materials cannot be constantly removed due to the instability of the cutting performance of the diamond wire. These phenomena are defined as the break-in characteristics of diamond wire. This paper focused on the break-in characteristics of diamond wire and the effects of these characteristics on the cutting performance. In an experiment, a single-wire sawing machine equipped with a monitoring system was used to analyze the horizontal and vertical cutting forces which arose during the cutting process. The cutting performance was evaluated by means of cutting profile measurements. The wires used were analyzed by the newly developed vision measurement system and through scanning electron microscope (SEM) imagery. On the basis of results, it was found that the break-in characteristics of diamond wire are strongly correlated with the wear behaviors of the diamond wire.

Porous silicon reorganization: Influence on the structure, surface roughness and strain

Porous silicon and epitaxial thickening is a lift-off approach for silicon foil fabrication to avoid kerf losses and produce foils with thicknesses less than 50µm. The crystal quality of the epitaxial silicon film strongly depends on the porous silicon template, which can be adapted through a reorganization process prior to epitaxy. In this work, we investigated the influence of reorganization on the structure of etched porous silicon layers. The reorganization processes were carried out in a quasi-inline Atmospheric Pressure Chemical Vapor Deposition reactor. Variations on the temperatures and process durations for the reorganization step were examined. The cross-sections showed that porous silicon requires temperatures of approximately 1150°C to produce an excellent template for epitaxy. Atomic Force Microscopy measurements on the samples annealed at different temperatures showed the evolution of the pores from as-etched to a closed surface. These measurements confirm that the surface is not yet closed after 30min of reorganization at 1000°C. Different durations of the reorganization step at a fixed temperature of 1150°C all lead to a closed surface with a comparable roughness of less than 0.5nm. X-ray diffraction measurements show a change in the strain in the porous layer from tensile to compressive when the reorganization temperature is increased from 800°C to 1150°C. A longer reorganization at a fixed temperature of 1150°C leads to a reduction in the strain without reducing the quality of the surface roughness. Defect density measurements on silicon layers deposited on those templates confirm an improvement of the template for longer reorganization times. This study shows that our porous silicon templates achieve lower surface roughness and strain values than those reported in other publications.

Epitaxial Growth of High Quality n-type Silicon Foils in a Quasi-inline APCVD Reactor

Reduction of solar cell fabrication costs is still of importance and can be achieved by going towards thinner silicon wafers. The aim is to achieve thicknesses in the range of100μm and below while avoiding further kerf loss. The approach using porous silicon as a sacrificial detachment layer and as a seed layer for epitaxial growth can accomplish that goal [1]. Several research groups have already shown the high potential of this technique[2]. Most processes have been conducted in microelectronic-grade batch or single-wafer reactors, questioning the industrial feasibility of this concept. In this work n-type silicon wafers, epitaxially grown in a quasi-inline Atmospheric Pressure Chemical Vapour Deposition (APCVD) reactor, will be presented. The wafers were characterized using confocal white light microscopy, quasi steady state photo conductance decay (QSSPC), microwave detected photo conductance decay (MWPCD) and spreading resistance profiling (SRP) measurements. The first batch of n-type wafers showed mean effective carrier lifetimes exceeding 100 μs on 45 x 45 mm2 and locally more than 300 μs. A detailed analysis on the thickness distribution, bulk lifetime and surface recombination velocity, affecting the effective carrier lifetime was conducted. For the second batch of n-type wafers mean effective carrier lifetimes of over 260 μs on 25 x25 mm2 and locally over 500 μs were determined. This corresponds to a local bulk lifetime of over 800 μs and shows the high material quality of epitaxial layers grown in our developed APCVD reactors.

Multi-Strata Stealth Dicing Before Grinding for Singulation-Defects Elimination and Die Strength Enhancement: Experiment and Simulation

We report on defects characterization and reduction as well as die strength enhancement using stealth dicing (SD) on high-backside reflectance (82%) 2-D NAND memory wafers. This is performed using three-strata subsurface infrared (1.342 μm) nanosecond pulsed laser die singulation with a partial-SD before grinding integration approach. In this paper, a combination of simulation, characterization, and optimization of the multi-strata SD process has led to the elimination of mechanical and absorptive laser singulation related defects such as frontside and backside surface ablation, and topside, backside, and edge chipping. At the same time, the kerf width and kerf straightness are robust against the effects of test element structures located along the dicing streets. There is a consistent coverage of high-quality SD kerf production with near-zero kerf loss across the 300 mm wafer. Multi-strata SD-unique defects such as interference effects and inter-strata cleavage plane {111} damage have been addressed. SD-related integrated defects including Si dust residue post-backgrinding and die attach film-related defects post-die separation have also been resolved. We illustrate the performance of this approach by demonstrating defect-free eight die stacks of 25 μm thick memory dies.

Multi-objective optimization for silicon wafer slicing using wire-EDM process

Abstract The existing silicon ingot slicing methods adopt contact forces in slicing that could easily cause higher kerf loss and a larger variation in the thickness of the sliced wafers. Wire-EDM is a potential process for slicing of silicon ingots into wafers. This work therefore demonstrates capability of wire-EDM in silicon wafer slicing through a RSM based experimentation involving use of molybdenum wires of 40–120 μm in diameter. During the experiments wafers of various height ranging from 50 to 150 mm were fabricated and capability of the process was assessed in minimizing the kerf width. It was evident that the kerf width reduces from 250 μm to 50 μm, when sliced by a 40 μm diameter wire, which amounts to a reduction in kerf loss by 300%. The slicing speed on the other hand could be increased by 40–50% to 2.5 mm/min over the conventional abrasive slicing. A multi-objective optimization methodology adopted gives parametric conditions that give minimum kerf width at the highest slicing speed and the lowest surface roughness.

High-Speed Dicing of SiC Wafers by Femtosecond Pulsed Laser

A novel dicing technology that utilizes femtosecond pulsed lasers (FSPLs) are demonstrated as a high-speed and cost-effective dicing process for SiC wafers. The developed dicing process consists of cleavage groove formation on a SiC wafer surface by the FSPL, followed by chip separation by pressing a cleavage blade. The effective FSPL scan speed on the SiC surfaces was 33 mm/s. Kerf loss can be negligible in the developed FSPL dicing process. In addition, the residual lattice strain in the FSPL-diced SiC chips was comparably small to that of the conventional mechanical process using diamond saws, due to the absence of the lattice heating effect in femtosecond-laser processes.

A rapid thermal process for silicon recycle and refining from cutting kerf-loss slurry waste

More than 40% of the high-purity silicon has been wasted as kerf loss during wafer slicing. This waste not only causes the environmental burden, but also increases the cost for silicon wafers. Although Si could be enriched easily to 85wt% from the waste, it was extremely difficult to further increase the purity of over 99wt% due to tiny SiC particles and metallic debris. We proposed a novel rapid thermal process, which was about one hundred times faster than the previous high-temperature treatment, to agglomerate Si in a couple minutes from the pretreated solid powder. With proper conditions, SiC particles and metals could be easily segregated to the surface of Si agglomerates. The high purity Si could be obtained by surface etching, and the best recycle yield was over 70%. The factors, such as temperature, holding time, and the surface oxidation of Si, were further discussed.

Effect of initial deflection of diamond wire on thickness variation of sapphire wafer in multi-wire saw

Sapphire wafers are widely used as substrates for fabricating gallium nitride light-emitting diodes. The quality of light-emitting diodes depends on the total thickness variation and BOW of the wafers. The multi-wire saw process is critical in determining post-processing times for steps such as diamond mechanical polishing and chemical mechanical polishing. In particular, thickness variation is affected by wear of diamond wires, which in turn is controlled by cutting conditions including wire speed, feed rate, initial contact condition between ingot and wire, and new wire consumption. Thickness variation shows a marked change from the initial to final feeding location during the multi-wire sawing process. A wire is not worn when it is initially contacted by an ingot. Hence, the initial kerf loss is greater than the kerf loss at the final feeding location. This study focused on minimizing the thickness variation between the initial and final contact points of the wafer. Experiments were conducted with different initial wire deflection conditions. The experimental results showed that increasing the wire deflection increased the cutting load, which in turn caused severe wear of the wire. Consequently, the thickness variation of the wafer in the multi-wire sawing process was controlled by adjusting the wire deflection.

New potential for reduction of kerf loss and wire consumption in multi-wire sawing

Wafer production with multi-wire sawing leads to a high consumption of wire and a relatively high offcut (kerf loss) of high purity silicon material. In this paper a new approach to reduce these costs in order to achieve a more cost efficient wafering is developed. Investigations of wire behavior during multi-wire sawing have been carried out at commercial multi wire-saws for large-scale production. Virgin and worn wire samples as well as silicon bricks were analyzed with regard to wear condition and diameter. These analyses revealed that material removal (abrasion) occurs mainly at one side of the wire. This suggests that no rotation of the wire around his longitudinal axis takes place during slicing. Because of these findings, a method was developed which is based on a wire with a non-circular cross-section. By this approach, a better exploitation of silicon material and wire can lead to a better cost-effectiveness of wafer and hence solar cells.

A Novel Approach of Reusing Kerf Loss Wastes in Preparation of <i>β-</i>SiC/Si<sub>2</sub>N<sub>2</sub>O Bonded SiC Refractory

A novel approach of reusing kerf loss wastes in preparation of β-SiC/Si2N2O bonded SiC refractory has been proposed. Thermodynamic analysis was conducted to prove the theoretical feasibility. β-SiC/Si2N2O bonded SiC refractory was successfully prepared at 1723K by adding kerf loss wastes replacing partial industrial SiC and Si powder on the condition of being buried with carbon. The β-SiC/Si2N2O bonded SiC refractory exhibited low porosity and excellent mechanical properties. Both Silicon powder in kerf loss wastes and industrial silicon powder formed β-SiC, Si2N2O and a small amount of SiO2. The approach proposed is beneficial for reducing the cost of preparation of SiC-based refractory as well as protecting the environment.

New Stress Activation Method for Kerfless Silicon Wafering Using Ag/Al and Epoxy Stress-Inducing Layers

The SLIM-cut technique provides a way to obtain thin silicon foils without a standard sawing step, thus avoiding kerf losses. This process consists of three steps: depositing a stress-inducing layer on top of the silicon surface; stress activation by heating and cooling, resulting in crack propagation in the silicon and detachment of a thin silicon layer; and a chemical cleaning to remove the stress-inducing layer. This paper describes a new stress activation method using Ag/Al and epoxy stress-inducing layers. The crack propagation is controlled along the sample length in order to avoid unwanted additional crack formation and interaction with other crack fronts. Silicon foils with thickness ranging between 50 and 130 μm were obtained with effective lifetimes between 1 and 81 μs.

Silicon recovery from cutting slurry by phase transfer separation

The cost of silicon feedstock is one of the most important factors for photovoltaic (PV) energy to reach grid parity. However, about 40% of high-purity silicon has been wasted as kerf loss during slicing. In the past decade, the recycle of silicon from the kerf-loss slurry waste has attracted much attention, but the progress is very slow. One of the technological challenges is the separation of SiC and Si particles. In this paper, a phase-transfer method using diesel based on the hydrophobicity difference between Si and SiC was proposed. SiC particles were enriched in the emulsion phase due to their more hydrophobic nature than Si. Si powder with a purity of 95wt% could be obtained, and the yield was about 80%. The factors, such as emulsification, affecting the separation efficiency were further discussed.

Characteristics of a Schottky Barrier Diode and the SiC Wafers Sliced by Wire Electrical Discharge Machining

The multi-wire electrical discharge slicing (multi-wire EDS), which is a brand-new method for fabricating wafers, is expected to considerably reduce the production cost of SiC wafers by decreasing in the width of kerf and kerf loss. We evaluated, for the first time, the influences of a wire electrical discharge machining (WEDM) on the SiC wafers based on experiments using WEDM equipped with a power supply of EDS. Although the analyses by transmission electron microscopy (TEM) and energy dispersive X-ray (EDX) revealed that the WEDM influenced layer consists of a contamination layer including several kinds of metals and a layer having crystal defects was certainly formed near the wafer surfaces, the width of the influenced layers was only 3μm, and the layer could be easily removed by the grinding process. Furthermore, characteristics of Schottky barrier diodes (SBDs) fabricated with removing the influenced layer formed by WEDM are comparable to those fabricated with using conventional wafers.

Effects of Machining Fluid on Electric Discharge Machining of SiC Ingot

Recently, ingots of silicon carbide have been adapted to be sliced by the wire-cut electrical discharge machining. Fast slicing, and the reduction in the loss are important for slicing of the wafer. In this paper, characteristic features of the electric discharge machining in the ion-exchange water and the fluorine-based fluid were compared for these improvement. The discharge was caused by a pulse voltage applied to a ingot of silicon carbide and the wire in machining fluid, and the slicing was proceeded. As a result, improvement of surface roughness and kerf loss was confirmed, for the first time. In addition, the improving methods for fast slicing were considered.

Dicing of SiC Wafer by Atmospheric-Pressure Plasma Etching Process with Slit Mask for Plasma Confinement

Silicon carbide (SiC) is a promising semiconductor material for high-temperature, high-frequency, high-power, and energy-saving applications. However, because of the hardness and chemical stability of SiC, few conventional machining methods can handle this material efficiently. A plasma chemical vaporization machining (PCVM) technique is an atmospheric-pressure plasma etching process. We previously proposed a novel style of PCVM dicing using slit apertures for plasma confinement, which in principle can achieve both a high removal rate and small kerf loss, and demonstration experiments were performed using a silicon wafer as a sample. In this research, some basic experiments were performed using 4H-SiC wafer as a sample, and a maximum removal rate of approximately 10 μm/min and a narrowest groove width of 25 μm were achieved. We also found that argon can be used for plasma generation instead of expensive helium gas.

Recovery of solar grade silicon from kerf loss slurry waste

Abstract During the last two decades and, particularly, in recent years, the photovoltaic sector has increased interest in the recovery of solar grade silicon (SOG). In order to further develop related technologies and to find suitable commercial applications for its recovery, it is essential to understand the current scientific know-how and advances. This review paper copes with recently published scientific articles in which the recovery of solar grade silicon has been studied. In addition, the present work provides an updated picture of the current understanding of the theory behind the employed technologies. The techniques discussed were divided into six categories, which are: (i) alloying process, (ii) hydrobromination, (iii) supercritical water, (iv) electrophoresis and gravitational settling, (v) directional solidification, and (vi) centrifugation.