Junctionless Transistor Research Articles

Impacts of Cavity Thickness and Insulating Material on Dielectric Modulated Trench Junction-less Double Gate Field Effect Transistor for Biosensing Applications

Introduction: This work represents the influence of gate dielectric, and the nano-cavity gap of a dielectric modulated trench gate Junction-less Double Gate Field Effect Transistor (JL-DGFET) on the different performance indicators is investigated considering the Low-Frequency Noise. Methods: It is noted that the gate dielectric and the nanogap, both parameters, have a substantial influence on the sensing capacity and performance of noise of the device. Results: A double gate suitable dielectric material and cavity thickness can effectively improve the biosensor’s sensitivity with a minimum amount of noise. Conclusion: The sensitivity is found to increase up to 9.5 for dielectric constant, k = 3.57 and 6.5 for dielectric constant, k = 2.1.

Subthreshold Drain Current Model of Cylindrical Gate All‐Around Junctionless Transistor With Three Different Gate Materials

ABSTRACTA novel subthreshold drain current model has been developed for a cylindrical gate all‐around junctionless transistor with three different gate materials. The proposed device is built with three gate regions of different work functions that effectively reduce the short‐channel effects caused by quantum mechanical effects. The drain current equation is solved for all three operating regions to investigate the device switching characteristics and minimize the drain‐induced barrier lowering (DIBL), velocity saturation, mobility degradation, and tunneling. It is understood that the triple material gate structure enhances the transport efficiency of the device. The proposed analytical model is validated by comparison with Sentaurus TCAD numerical simulator results and good agreement is found to be achieved.

Effect of copper doping on zinc oxide for potential use in nanowire devices

AbstractZinc oxide is a promising material in semiconductor research owing to its exceptional properties including wide band gap and high carrier mobility. We observe the effect of copper (a promising acceptor species) doping properties of zinc oxide using Density Functional Theory (DFT). Carrier concentration calculations reveal that the copper doping leads to a p-type semiconductor with an increase in hole concentration to the order of 1018 cm−3. The resultant structure is used to build junctionless nanowire transistors. These nanoscale devices exhibit excellent characteristics including a diameter-normalized on-current of more than 500 μA/μm and an on-current to off-current ratio of greater than 5 × 106 for select configurations. In addition, several design parameters are varied, and guidelines are presented that offer improved performance. Graphical abstract Fig. a Copper-doped zinc oxide junctionless transistor (UL represents source/drain underlap) b Cross-sectional view c Drain current vs gate voltage for one of the devices

Gate-driven transition temperatures of electron hopping behaviors in Hubbard bands formed by dopant-induced QD array in silicon nanowire

Abstract Dopant atoms confined in silicon nanoscale channel can be ionized to form quantum dots (QDs). Several dopant atoms couple with each other forming energy bands, where the electron hopping behavior can be described by the Hubbard model. This characteristic renders dopant-induced QDs particularly appealing for applications in nanoelectronic and quantum devices. Herein we study the gate-driven transition temperatures of electron hopping behavior in the upper Hubbard bands (UHBs) and lower Hubbard bands (LHBs) formed by dopant-induced QD array in junctionless silicon nanowire transistors. The gate-dependent transition temperatures are calculated for three stages of electron hopping behaviors including Efros–Shklovskii Variable Range Hopping (ES-VRH), Mott VRH and Nearest Neighbor Hopping (NNH). Our experimental results indicate that the ES-VRH in arrays of dopant atoms occurs in the domination of a long-range Coulomb interaction, in which the hopping distance relies on the Coulomb gap. Furthermore, the localization length of ES-VRH can be modulated by gate voltages. Those factors lead to the significant difference of transition temperatures between the UHBs and LHBs. In addition, we find that the source–drain bias voltage can effectively modulate the transition temperatures between VRH and NNH by thermal activation energies under different bias voltages Vds.

Performance Analysis of JL-FinFET with Varied Non-Uniform Doping Concentrations, Fin Height and Fin Width using Device Simulator

With the growth of the MOSFET technology, the size of the transistor becomes smaller which can lead to Short-Channel Effects (SCEs). In order to address the SCEs, multi-gate transistor such as Fin Field-Effect Transistor (FinFET) has been invented. Meanwhile, it is found that the conventional transistor with junctions also has its drawbacks and limitations due to the decrease in the gate length. The SCEs can occur and affect the overall performance of the device with lower switching times and lower current density . In order to address these limitations, new structure of transistor without junction known as a junctionless (JL) transistor has been proposed. In this work, the impact of uniform versus non-uniform doping concentrations, fin height (Hfin) and fin width (Wfin) in JL-FinFET were investigated by using Technology Computer Aided Design (TCAD) Tools. It was found that non-uniform doping concentration of 4 x1018 cm-3 for the source/drain and of 4 x1017 cm-3 for the channel, together with Hfin of 20 nm and Wfin of 4 nm provide the best electrical performance of Ioff = 6.45 x10-17 A, Ion = 6.14 x10-6 A, Ion/Ioff = 9.52 x1010 and DIBL = 11 mV/V. The outcome of this research work can be used as a basis to understand JL-FinFET biosensors for medical applications and more complex JL structures.

Core-shell architecture and channel suppression: unleashing the potential of SC_RCS_DGJLFET

In this investigation, a suppressed channel-rectangular core–shell double gate junctionless field effect transistor (SC_RCS_DGJLFET) is simulated to enhance the junctionless device’s performance. This study leverages a core–shell architecture and channel suppression technique to improve the gate controllability over the channel region which helps in substantial depletion of the shells in the OFF state of the device. When compared to conventional double gate JLFETs (C_DGJLFET) and rectangular core–shell double gate JLFETs (RCS_DGJLFET), the performance of the SC_RCS_DGJLFET is superior in terms of IOFF, ION/IOFF ratio, DIBL and subthreshold slope (SS). The SC_RCS_DGJLFET achieves an ultra-low IOFF of 7.033 × 10−16 A, indicating a low leakage current with an impressive ION/IOFF = 5.092 × 1011 . Other performance parameters such as subthreshold slope and DIBL has also been improved for the SC_RCS_DGJLFET device. Subthreshold slope has been decresesd by 4.76% whereas the DIBL decreased by 33.82% when compared to existing RCS_DGJLFET. Additionally, to analyze the effect of doping on the device performance, the core doping in SC_RCS_DGJLFET is varied for fixed shell doping. The study found that fixing core doping to an appropriate value is a crucial parameter to achieve good device performance. The impact of variation of oxide extension towards the source and drain LextS/LextD in SC_RCS_DGJLFET is also studied for the first time in the core–shell architecture which has further improved the device’s performance. Finally, a CMOS inverter is designed using the proposed device that provides valuable insights into its suitability for digital circuit applications and verifies its performance benefits compared to existing transistor technologies. The SC_RCS_DGJLFET based CMOS inverter shows a sharp transition in voltage transfer characteristics (VTC), indicating fast switching speed and precise signal processing capabilities when compared to a CMOS inverter based on a conventional double gate junctionless field effect transistor (C_DGJLFET). Moreover, the transient characteristics of the SC_RCS_DGJLFET based CMOS inverter exhibit an improved output voltage swing, suggesting enhanced dynamic behaviour and stability during logic state transitions.

Analysis of 10 nm Strained Channel Double Gate Ultra-Thin Body Junctionless MOSFET

Numerous technological improvements and innovative device architecture have been thoroughly explored and tested for continually downscaling components without compromising on performance metrics. The most simplified structure that has been introduced so far is the junctionless transistors. Junctionless transistors have been shown to exhibit excellent electrical behavior with improved short-channel effects. The major challenges with junctionless based transistors are low ON-current drive and high device variability. Strain engineering has been proven to be a viable option to enhance the ON-current performance of the MOSFET. This work incorporated strained silicon in double gate junctionless ultra-thin body MOSFET (DG-JL UTB MOSFET), which enhanced the mobility of the charge carrier as a result of which ON current behavior improves. The simulated results show 30.2% enhancement in the ON-current, subthreshold current reduced to nearly half, ION/IOFF ratio is increased by three times, and Drain-induced barrier lowering (DIBL) reduced by 25.1% with respect to unstrained device. Analog performance metrics are also calculated for the considered device design. With strained silicon, the value of Gm is increased by more than 30% and transconductance generation factor (TGF) is increased by 28.27% in reference with the unstrained device.

Sensitivity analysis of methanol, chloroform, and dichloromethane using GAA-JLT-based gas sensor

Owing to the fact that the gate-all-around architecture is expected to prevail in the upcoming technology nodes, in this work we have taken up a simulation-based investigation on design of a gate-all-around junctionless transistor (GAA-JLT) based label-free gas sensor with conducting polymer (CP) gate. In the initial part of our work we have focused on the variation n device and sensor performance with initial work function of the CP, which depends upon its growth condition and primary doping. Interaction with various test gases modifies the CP characteristics, thereby changing its work function. Due to this a change in device characteristics is observed, which serves as the metric for assessing the GAA-JLT-based gas sensor performance. We have investigated the variation in device characteristics in the presence of different test gases. Further, the variation in sensor performance on interaction with the different test gases has been examined. The impact of operating conditions such as ambient temperature and partial pressure of the test gas on the sensing performance has been investigated. The impact of device dimension on the sensing performance has also been evaluated. Our computations reflect that tuning the initial work function of the CP by choosing the proper primary dopant concentration model along with proper tuning of the operating conditions can enhance the performance accuracy of the sensor.

Study of performance evaluation of various characteristics of a single phase full bridge inverter circuit using surrounded channel junctionless field effect transistor

This paper reports the characteristics study of a single phase full bridge power electronic inverter circuit with a new type of technology namely surrounded channel junctionless field effect transistor (SCJLFET) as a switch. The inverter circuit has been designed using mixed mode simulation platform of TCAD device simulator. The transient characteristics for various temperatures and work functions have been analysed. In the steady state analysis the output current and voltage variation with input voltage with various temperatures and work functions have been studied. The power factor variations with gate oxide thickness and dielectric constant of gate dielectric. The simulation and designing process along with pros and cons have been characterized. The SCJLFET would be one of the strongest participants for advanced power electronics technology as a switches, with various virtues of high-speed operation, low power consumption and low budget process integration. It has also been found that single phase full bridge inverter is giving best results when made using SCJLFET.

Impact of varying channel length on Analog/RF performances in a novel n-type silicon-based DG-JLT

Shrinking MOSFETs suffer performance hits due to short-channel effects and leakage. Junctionless transistors JLTs emerge as promising alternatives due to simpler fabrication and better gate control. This paper investigates the analog and RF performance characteristics of n-type Silicon-Based Double Gate Junctionless Transistors with varying channel lengths (15 nm, 20 nm, and 25 nm) This study evaluates analog device performance through critical parameters: drain current density (Id), transconductance (gm), output resistance (RO), intrinsic gain (gmRO), and transconductance generation factor (gm/Id). These parameters assess current handling, gain characteristics, and design efficiency, providing a comprehensive analysis for analog circuit applications. Results indicate that the device having 15 nm channel length exhibits a transconductance which is 25.38 % more than the 20 nm variant and drain current which is 44.7 % more than the latter, suggesting its superior performance to devices with longer channel lengths. In addition, the RF performance of the devices is evaluated using the small signal model of the device. This work further investigates the high-frequency response of the devices using key figures of merit (FoMs): gate capacitances (Cgs, Cgd, Cgg), cut-off frequency (fT), and maximum oscillation frequency (fMAX). These parameters quantify the influence of parasitic capacitances on switching speed and the maximum useable frequency for analog and RF applications. Analyzing Cgs, Cgd, and Cgg reveals the impact of gate control on high-frequency operation. The device having 15 nm channel length, exhibits an increase of 47.29 % in fT and 68.97 % increase in fMAX compared to device having 20 nm channel length. The findings underscore the significance of channel length optimization in enhancing the Analog and RF performance of n-type Silicon-based Double Gate Junctionless Transistors.

Performance enhancement of nanotube junctionless FETs with low doping concentration rings

To reduce the static power consumption of the NT JLFET and the effect of SCEs on the NT JLFET, A nanotube junctionless field effect transistor with cyclic low doping concentration regions (C NT JLFET) is proposed. Based on Sentaurus TCAD numerical simulations, the electrical properties of the C NT JLFET and the NT JLFET were comparatively investigated, and the effects of the length (L CD) and radius (R CD) of cyclic low doping concentration regions on the electrical properties of the C NT JLFETs were studied. The C NT JLFET reduces the gate-induced drain leakage (GIDL) due to lateral band-to-band-tunneling (L-BTBT) as compared to the NT JLFET. As the L CD or R CD increases, the off-state current decreases. In addition, the C NT JLFET suffers from fewer short channel effects (SCEs), such as threshold voltage roll-off, drain-induced barrier lowering and subthreshold swing deterioration, compared to the NT JLFET. The inhibition of L-BTBT and attenuation of SCEs by cyclic low doping concentration regions remains when the channel length of the C NT JLFET is shortened to 10 nm. The C NT JLFET are suitable for low power applications as they exhibit reduced L-BTBT and suffer from fewer SCEs.

Linearity and intermodulation distortion analysis of single and dual metal gate junctionless transistor

Linearity and intermodulation distortion are very crucial parameters for RFICs design. Therefore, in this work, a detailed comparative analysis on linearity and intermodulation distortion of single metal (SMG) and double metal (DMG) double gate junction less transistor (JLT) is done using TCAD silvaco suite. Furthermore, the effects of temperature fluctuation, gate length variation, and gate material engineering on the linearity performance of both devices are also studied. A few significant figures of merit, including Voltage Intercept Point 2 (VIP2), Voltage Intercept Point 3 (VIP3), Third Order Intercept Power (IIP3), 1 dB Compression Point (P1dB), Third Order Intermodulation Distortion (IMD3), and the transconductance derivative parameters First Order Transconductance (gm1), Second Order Transconductance (gm2), and Third Order Transconductance (gm3) are used to assess the device linearity and intermodulation distortion of SMG and DMG JLT's. The findings show that higher VIP2, VIP3, IIP3, 1-dB compression point and lower gm3, IMD3 values are obtained for the SMG JLT device when compared to its counterpart DMG JLT. SMG JLT, which assures strong linearity and low distortion.

Proposal for variability-induced effective radius of elliptical gate-all-around junctionless transistors and its applicability in hydrogen gas sensors

Nano-ribbons with gate-all-around (GAA) architecture have been predicted to serve as next-generation on-chip transistors, among which, the junctionless transistor (JLT) has emerged as a promising candidate, mitigating few limitations of conventional inversion-mode metal–oxide–semiconductor field-effect transistors (MOSFETs). Due to imperfect fabrication process, the GAA architecture is often subject to cross-sectional variabilities. This work presents an analytical model for the effective radius of elliptical cross-section of the channel region having a non-circular oxide surrounding it, resulting in various structural configurations having non-uniform oxide thickness. To demonstrate the impact of cross-sectional variability of GAA-JLTs, few performance parameters, such as, drain current, threshold voltage, and so on, have been evaluated using our proposed formulation for the effective radius and the results were found to agree well with TCAD simulations. As a case study, we have emphasized on the applicability of our proposed model in variability-induced GAA-JLT-based hydrogen sensors using few sensitivity metrics. Our computations show substantial changes in the sensing device as the cross-section deviates from the ideal circular one. Our computations reveal that incorporating the effects of radius variability in the device model along with proper tuning of operating conditions can enhance the performance and accuracy of such sensors.

TCAD simulation study of heavy ion radiation effects on hetero junctionless tunnel field effect transistor

Semiconductor devices used in radiation environment are more prone to degradation in device performance. Junctionless Tunnel Field Effect Transistor (JLTFET) is one of the most potential candidates which overcomes the short channel effects and fabrication difficulties. In this work, 20 nm JLTFET is proposed with Silicon in the drain/channel region whereas source uses different materials, Silicon Germanium (SiGe), Gallium Nitride (GaN), Gallium Arsenide (GaAs), Indium Arsenide (InAs). The device performance is examined by subjecting it to heavy ion radiation at a lower and higher dose of linear energy transfer (LET) values. It can be seen that the most sensitive location is the source/channel (S/C) interface for SiGe, GaN and GaAs whereas the drain/channel (D/C) interface for InAs. Further analysis is carried out at these vulnerable regions by matching ION of all materials. The parameters, transient peak current (Ipeak), collected charge (QC), threshold voltage shift (ΔVth) and bipolar gain (β) are extracted using transient simulations. It is observed that for a lower dose of LET, Ipeak of SiGe is 27% lesser than InAs and for higher dose of LET, SiGe shows 56% lesser Ipeak than InAs. SiGe is less sensitive at lower and higher dose of LET due to reduced ΔVth, tunneling and electron density.

Trench Dual Gate Junctionless Field Effect Transistor

Diversified biomolecules sensing is turning out to be the most promising area of research due to ever decreasing healthy lifestyle. Field effect transistorized biosensing approach puts its signature as label free, portable and also very careful pathway. In this present work a trench structured dielectric modulated double gate junction-less field effect transistor (TG-DMJLFET) is urbanized using SILVACO ATLAS simulator for label free detection of biomolecules. The developed structure has two vertically positioned gates in distinct trenches. For immobilizing biomolecules, two cavities are formed in the gate oxide region for dielectric modulation. The dielectric constant (k) has been varied over a wide range of 1.54 (Uricase) to 12(Gelatin) signifying the sensing of diverse charged biomolecules. The sensitivity is evaluated in terms of threshold voltage shift and transconductance . The in-depth electrostatic analysis is illustrated in terms of central potential ,energy band diagram ,drive current and also by the depiction of the electric field .In case of charged biomolecules, the shift in threshold voltage is obtained as 350 mV for change in the di-electric constant (k) ranging from 1.54 to 12. The transconductance alteration is observed as 1.94×10-5 when the k is changed from 3.46 to 12 .The device has showed excellent performance in biomolecules sensing.

DESIGN AND ANALYSIS OF ELECTRICAL CHARACTERISTICS OF INVERTED-T JUNCTIONLESS (JL) FET THROUGH GEOMETRIC AND PROCESS VARIATIONS FOR HIGH FREQUENCY APPLICATIONS

An inverted-T structure is implemented with the Junctionless (JL) topology at nanoscale dimensions. The Inverted-T Junctionless (ITJL) FET features a multi-fin architecture that utilizes the unused space within the fins and combines it with the junctionless topology, maintaining the same doping concentration from source to drain. In order to mitigate the short channel effects and overcome the fabrication challenges, an inverted-T FET has been designed. The crucial performance parameters of device are explored by varying the geometric dimensions and process parameters. The performance of ITJLFET is measured by varying different parameters namely temperature (T), doping concentration (Nd), work function 𝒎 ), and dielectric constant (K) at 30-nm technology node and effect of geometric variations are measured by altering the gate length (Lg) and oxide thickness (Tox). Inverted-T junctionless field effect transistor (ITJLFET) is designed with different gate lengths in the range of 14 nm to 30 nm and shows the improvement in ION by 64% as compared to the conventional JLFET. The parametric analysis like transfer characteristics (Id-Vgs), Ion/IOFF ratio, subthreshold swing (SS), drain induced barrier lowering (DIBL) and gate capacitance (Cgg) are investigated for 250 K to 350 K. From the results, it is perceived that temperature has less effect on the Inverted-T junctionless transistor performance. The cut-off frequency for the designed device is calculated and observed to be in the range of 0.3 to 1.5 THz. Hence, device can be used for high-frequency applications at the submicron regime.

Quantum and classical simulation of core shell based junctionless field effect transistor with digital application

The detailed performance analysis of core–shell Gate All Around junctionless field effect transistor along with CMOS inverter as an application with quantum models is presented in this paper for the first time. To appreciate the performance of the device and the application even at smaller channel length, the comparison with classical models is also presented. The OFF current was calculated as 3.68 × 10−16A on incorporating the quantum models. The subthreshold swing (SS) and Drain induced barrier lowering (DIBL) are found to be near ideal values. The SS and DIBL was calculated as 62.82 mV/dec and 33.4 mV/V. The DIBL was found to be lesser by 52.82% with quantum model than classical model. The performance obtained using quantum models are better than the classical models in terms of different parameters such as OFF current, ON current, SS, DIBL, threshold voltage, transconductance. Further, the performance of the CMOS inverter with quantum models by considering the n-type and p-type core–shell Gate All Around junctionless field effect transistor is also presented . The OFF current of p-type and n-type was matched before designing the application. A sharp transfer characteristics of the CMOS inverter is obtained. The performance was also studied by calculating the drain current from each of p-type and n-type and found to be more than 1 × 10−7A and SNM (Static Noise Margin) was calculated as 267 mV. The transient response of CMOS inverter exhibits the potential of CMOS inverter using the proposed device even at smaller channel lengths.

Electrostatically Doped Junctionless Graphene Nanoribbon Tunnel Field-Effect Transistor for High-Performance Gas Sensing Applications: Leveraging Doping Gates for Multi-Gas Detection.

In this paper, a new junctionless graphene nanoribbon tunnel field-effect transistor (JLGNR TFET) is proposed as a multi-gas nanosensor. The nanosensor has been computationally assessed using a quantum simulation based on the self-consistent solutions of the mode space non-equilibrium Green's function (NEGF) formalism coupled with the Poisson's equation considering ballistic transport conditions. The proposed multi-gas nanosensor is endowed with two top gates ensuring both reservoirs' doping and multi-gas sensing. The investigations have included the IDS-VGS transfer characteristics, the gas-induced electrostatic modulations, subthreshold swing, and sensitivity. The order of change in drain current has been considered as a sensitivity metric. The underlying physics of the proposed JLGNR TFET-based multi-gas nanosensor has also been studied through the analysis of the band diagrams behavior and the energy-position-resolved current spectrum. It has been found that the gas-induced work function modulation of the source (drain) gate affects the n-type (p-type) conduction branch by modulating the band-to-band tunneling (BTBT) while the p-type (n-type) conduction branch still unaffected forming a kind of high selectivity from operating regime point of view. The high sensitivity has been recorded in subthermionic subthreshold swing (SS < 60 mV/dec) regime considering small gas-induced gate work function modulation. In addition, advanced simulations have been performed for the detection of two different types of gases separately and simultaneously, where high-performance has been recorded in terms of sensitivity, selectivity, and electrical behavior. The proposed detection approach, which is viable, innovative, simple, and efficient, can be applied using other types of junctionless tunneling field-effect transistors with emerging channel nanomaterials such as the transition metal dichalcogenides materials. The proposed JLGNRTFET-based multi-gas nanosensor is not limited to two specific gases but can also detect other gases by employing appropriate gate materials in terms of selectivity.

Capacitorless One-Transistor Dynamic Random-Access Memory with Novel Mechanism: Self-Refreshing.

In this paper, we propose for the first time a self-refreshing mechanism in a junctionless field-effect transistor (JLFET) based on one-transistor dynamic random-access memory (1T-DRAM) with a silicon-on-insulator (SOI) structure. The self-refreshing mechanism continuously creates holes by appropriately generating impact ionization during the holding process through the application of an appropriate operation bias voltage. This leads to self-refreshing, which prevents the recombination of holes. When using the self-refreshing mechanism for the proposed device, the sensing margins were 15.4 and 12.7 μA/μm at 300 and 358 K, respectively. Moreover, the device achieved an excellent performance retention time of >500 ms, regardless of the temperature of the 1T-DRAM with a single gate. Furthermore, cell disturbance analysis and voltage optimization were performed to evaluate the in-cell reliability of the proposed device. It also showed excellent performance in terms of energy consumption and writing speed.

Impact of Transport Mechanism on Binding Kinematics and Sensitivity of FET Biosensors

In this work, the impact of bioanalyte concentration and the dominant transport mechanism of biomolecules on the binding kinematics of the target biomolecules at the sensing surface have been investigated in detail. A comprehensive analysis of the fundamental parameters such as equilibrium response time and equilibrium density of the binding molecules at the sensing surface considering different concentrations of the analytes and their transport mechanisms has been performed. The impact of these realistic artifacts on the current sensitivity of emerging junctionless field effect transistors (JLFETs) and tunnel field effect transistors (TFETs)-based ion-sensitive field effect transistor (ISFET) has been investigated. Moreover, depending on the bioanalyte concentration, design guidelines for the dimensions of the sensing surface have been provided for a minimum limit of detection (LOD). The impact of charge screening and nonspecific binding on current sensitivity has also been discussed in depth. We believe that the guidelines presented in this work will enable the community to conceptualize, understand, and design novel label-free biosensors more rationally considering the practical scenario.