Junctionless Field Effect Transistor Research Articles

Performance enhancement of nanotube junctionless FETs with low doping concentration rings

Abstract To reduce the static power consumption of the NT JLFET and the effect of SCEs on the NT JLFET, A nanotube junctionless field effect transistor with cyclic low doping concentration regions (C NT JLFET) is proposed. Based on Sentaurus TCAD numerical simulations, the electrical properties of the C NT JLFET and the NT JLFET were comparatively investigated, and the effects of the length (LCD) and radius (RCD) of cyclic low doping concentration regions on the electrical properties of the C NT JLFETs were studied. The C NT JLFET reduces the gate-induced drain leakage (GIDL) due to lateral band-to-band-tunneling (L-BTBT) as compared to the NT JLFET. As the LCD or RCD increases, the off-state current decreases. In addition, the C NT JLFET suffers from fewer short channel effects (SCEs), such as threshold voltage roll-off, drain-induced barrier lowering and subthreshold swing deterioration, compared to the NT JLFET. The inhibition of L-BTBT and attenuation of SCEs by cyclic low doping concentration regions remains when the channel length of the C NT JLFET is shortened to 10 nm. The C NT JLFET are suitable for low power applications as they exhibit reduced L-BTBT and suffer from fewer SCEs.

Piezoresistive sensitivity enhancement below threshold voltage in sub-5 nm node using junctionless multi-nanosheet FETs.

In this paper, the piezoresistive sensitivity is enhanced by applying uniform mechanical stress (MS) on the multi-nanosheet (NS) channels of sub-5 nm junctionless field-effect transistors (FETs). The piezoresistivity of the sensing device is boosted by narrowing channel conductivity using low gate biasing and reducing physical channel width, resulting in the maximum (~6 times higher) sensitivity observed in the subthreshold regime compared to the ON-state condition. In addition, the sensitivity is extensively increased by ~30.3% near the threshold voltage (VTH) with horizontally multi-NS stacking due to the uniform MS distribution on the multi-NS channels, which can sense slight deflection of pressure on the circular diaphragm. These results show that the tunable sensitivity of junctionless multi-channel devices is superior to the inversion mode, a consequence of the less scattering effect, better thermal stability, and low electronic noise.

An analytical model of P+ SiC core-shell JLFETs to analyze the performance for higher breakdown voltages applications

In this article, we proposed a core-shell (CS) architecture that uses the silicon carbide (SiC) as a nanowire for higher breakdown voltages in a Junctionless field effect transistor (JLFET). The P+ core-shell improves the electrostatic integrity and reduces lateral band-to-band tunneling in SiC JLFET. Furthermore, the SiC is wide band gap material which helps to achieve the full volume depletion in JLFET at such short channel lengths. Thus, the OFF-state current in P+ SiC CS JLFET has reduced to 10−16 μA even at temperature 600 K and VDS = 2.0 V. The P+ SiC CS JLFET shows significant performance even at higher drain voltages. Hence, we investigate the P+ SiC CS JLFET for higher breakdown voltages with the impact of higher temperatures. In addition, the impact of higher drain voltages with higher temperatures is also examined. This paper presents an analytical model for P+ SiC CS JLFETs which considers Poisson's equation for nanowires as well as the surface potential at the threshold voltage (Vth) and electric field at the zero point (Ez). The model shows that the surface potential and the electric fields in nanowires are essential for an accurate estimation of the drain current. In addition to the numerical modeling results provided by SILVACO TCAD, the performance of the proposed analytical model was compared with simulation results. The results showed good agreement between the simulations and the proposed compact model. This indicates that the proposed model can be used to provide accurate drain current predictions in nanoscale transistors.

Trench Dual Gate Junctionless Field Effect Transistor

Diversified biomolecules sensing is turning out to be the most promising area of research due to ever decreasing healthy lifestyle. Field effect transistorized biosensing approach puts its signature as label free, portable and also very careful pathway. In this present work a trench structured dielectric modulated double gate junction-less field effect transistor (TG-DMJLFET) is urbanized using SILVACO ATLAS simulator for label free detection of biomolecules. The developed structure has two vertically positioned gates in distinct trenches. For immobilizing biomolecules, two cavities are formed in the gate oxide region for dielectric modulation. The dielectric constant (k) has been varied over a wide range of 1.54 (Uricase) to 12(Gelatin) signifying the sensing of diverse charged biomolecules. The sensitivity is evaluated in terms of threshold voltage shift and transconductance . The in-depth electrostatic analysis is illustrated in terms of central potential ,energy band diagram ,drive current and also by the depiction of the electric field .In case of charged biomolecules, the shift in threshold voltage is obtained as 350 mV for change in the di-electric constant (k) ranging from 1.54 to 12. The transconductance alteration is observed as 1.94×10-5 when the k is changed from 3.46 to 12 .The device has showed excellent performance in biomolecules sensing.

DESIGN AND ANALYSIS OF ELECTRICAL CHARACTERISTICS OF INVERTED-T JUNCTIONLESS (JL) FET THROUGH GEOMETRIC AND PROCESS VARIATIONS FOR HIGH FREQUENCY APPLICATIONS

An inverted-T structure is implemented with the Junctionless (JL) topology at nanoscale dimensions. The Inverted-T Junctionless (ITJL) FET features a multi-fin architecture that utilizes the unused space within the fins and combines it with the junctionless topology, maintaining the same doping concentration from source to drain. In order to mitigate the short channel effects and overcome the fabrication challenges, an inverted-T FET has been designed. The crucial performance parameters of device are explored by varying the geometric dimensions and process parameters. The performance of ITJLFET is measured by varying different parameters namely temperature (T), doping concentration (Nd), work function 𝒎 ), and dielectric constant (K) at 30-nm technology node and effect of geometric variations are measured by altering the gate length (Lg) and oxide thickness (Tox). Inverted-T junctionless field effect transistor (ITJLFET) is designed with different gate lengths in the range of 14 nm to 30 nm and shows the improvement in ION by 64% as compared to the conventional JLFET. The parametric analysis like transfer characteristics (Id-Vgs), Ion/IOFF ratio, subthreshold swing (SS), drain induced barrier lowering (DIBL) and gate capacitance (Cgg) are investigated for 250 K to 350 K. From the results, it is perceived that temperature has less effect on the Inverted-T junctionless transistor performance. The cut-off frequency for the designed device is calculated and observed to be in the range of 0.3 to 1.5 THz. Hence, device can be used for high-frequency applications at the submicron regime.

Quantum and classical simulation of core shell based junctionless field effect transistor with digital application

The detailed performance analysis of core–shell Gate All Around junctionless field effect transistor along with CMOS inverter as an application with quantum models is presented in this paper for the first time. To appreciate the performance of the device and the application even at smaller channel length, the comparison with classical models is also presented. The OFF current was calculated as 3.68 × 10−16A on incorporating the quantum models. The subthreshold swing (SS) and Drain induced barrier lowering (DIBL) are found to be near ideal values. The SS and DIBL was calculated as 62.82 mV/dec and 33.4 mV/V. The DIBL was found to be lesser by 52.82% with quantum model than classical model. The performance obtained using quantum models are better than the classical models in terms of different parameters such as OFF current, ON current, SS, DIBL, threshold voltage, transconductance. Further, the performance of the CMOS inverter with quantum models by considering the n-type and p-type core–shell Gate All Around junctionless field effect transistor is also presented . The OFF current of p-type and n-type was matched before designing the application. A sharp transfer characteristics of the CMOS inverter is obtained. The performance was also studied by calculating the drain current from each of p-type and n-type and found to be more than 1 × 10−7A and SNM (Static Noise Margin) was calculated as 267 mV. The transient response of CMOS inverter exhibits the potential of CMOS inverter using the proposed device even at smaller channel lengths.

Electrostatically Doped Junctionless Graphene Nanoribbon Tunnel Field-Effect Transistor for High-Performance Gas Sensing Applications: Leveraging Doping Gates for Multi-Gas Detection.

In this paper, a new junctionless graphene nanoribbon tunnel field-effect transistor (JLGNR TFET) is proposed as a multi-gas nanosensor. The nanosensor has been computationally assessed using a quantum simulation based on the self-consistent solutions of the mode space non-equilibrium Green's function (NEGF) formalism coupled with the Poisson's equation considering ballistic transport conditions. The proposed multi-gas nanosensor is endowed with two top gates ensuring both reservoirs' doping and multi-gas sensing. The investigations have included the IDS-VGS transfer characteristics, the gas-induced electrostatic modulations, subthreshold swing, and sensitivity. The order of change in drain current has been considered as a sensitivity metric. The underlying physics of the proposed JLGNR TFET-based multi-gas nanosensor has also been studied through the analysis of the band diagrams behavior and the energy-position-resolved current spectrum. It has been found that the gas-induced work function modulation of the source (drain) gate affects the n-type (p-type) conduction branch by modulating the band-to-band tunneling (BTBT) while the p-type (n-type) conduction branch still unaffected forming a kind of high selectivity from operating regime point of view. The high sensitivity has been recorded in subthermionic subthreshold swing (SS < 60 mV/dec) regime considering small gas-induced gate work function modulation. In addition, advanced simulations have been performed for the detection of two different types of gases separately and simultaneously, where high-performance has been recorded in terms of sensitivity, selectivity, and electrical behavior. The proposed detection approach, which is viable, innovative, simple, and efficient, can be applied using other types of junctionless tunneling field-effect transistors with emerging channel nanomaterials such as the transition metal dichalcogenides materials. The proposed JLGNRTFET-based multi-gas nanosensor is not limited to two specific gases but can also detect other gases by employing appropriate gate materials in terms of selectivity.

Performance Evaluation of Junctionless Cylindrical Gate-All-Around FET for Low Power Applications

The advent of device miniaturization techniques and the evolution of very deep submicron technology have led to the increased prominence of short channel effects (SCEs) in conventional transistors (CTs). Now, in the era of nanoengineering and nano-wires, current research is centered around a novel device known as the Junctionless Field Effect Transistor (JLFET), which incorporates gate-all-around engineering applications. Given the challenges associated with scaling transistor sizes, such as creating high-quality junctions and changing doping concentrations (~1019 cm–3) over a 10 nm distance, JLFET emerges as a promising alternative to CTs. Notably, JLFET lacks junctions and doping concentration gradients. In this study, the authors have conducted a comprehensive analysis and performance evaluation of JLFET and CTs, specifically in the context of low-power applications. Various performance parameters of JLFET, including SS, DIBL, transconductance, output conductance, and Ion/Ioff, have been assessed. The findings indicate that JLFET exhibits reduced susceptibility to SCEs compared to CTs and demonstrates exceptional current driving capability.

Capacitorless One-Transistor Dynamic Random-Access Memory with Novel Mechanism: Self-Refreshing.

In this paper, we propose for the first time a self-refreshing mechanism in a junctionless field-effect transistor (JLFET) based on one-transistor dynamic random-access memory (1T-DRAM) with a silicon-on-insulator (SOI) structure. The self-refreshing mechanism continuously creates holes by appropriately generating impact ionization during the holding process through the application of an appropriate operation bias voltage. This leads to self-refreshing, which prevents the recombination of holes. When using the self-refreshing mechanism for the proposed device, the sensing margins were 15.4 and 12.7 μA/μm at 300 and 358 K, respectively. Moreover, the device achieved an excellent performance retention time of >500 ms, regardless of the temperature of the 1T-DRAM with a single gate. Furthermore, cell disturbance analysis and voltage optimization were performed to evaluate the in-cell reliability of the proposed device. It also showed excellent performance in terms of energy consumption and writing speed.

Impact of Transport Mechanism on Binding Kinematics and Sensitivity of FET Biosensors

In this work, the impact of bioanalyte concentration and the dominant transport mechanism of biomolecules on the binding kinematics of the target biomolecules at the sensing surface have been investigated in detail. A comprehensive analysis of the fundamental parameters such as equilibrium response time and equilibrium density of the binding molecules at the sensing surface considering different concentrations of the analytes and their transport mechanisms has been performed. The impact of these realistic artifacts on the current sensitivity of emerging junctionless field effect transistors (JLFETs) and tunnel field effect transistors (TFETs)-based ion-sensitive field effect transistor (ISFET) has been investigated. Moreover, depending on the bioanalyte concentration, design guidelines for the dimensions of the sensing surface have been provided for a minimum limit of detection (LOD). The impact of charge screening and nonspecific binding on current sensitivity has also been discussed in depth. We believe that the guidelines presented in this work will enable the community to conceptualize, understand, and design novel label-free biosensors more rationally considering the practical scenario.

TCAD based investigation of junctionless phototransistor for UVC radiation detection

In this study, a gallium oxide gated junctionless phototransistor has been proposed for the first time for deep ultraviolet (210–280 nm) solar blind radiation (UVC) detection. The inherent optical property of gallium oxide has been utilized here to absorb deep ultraviolet radiation. It is designed as a photo absorber layer over the complete channel of the junctionless field effect transistor. Here, the conduction material is silicon (source, channel, and drain), which is entirely separated by the photo absorber (gallium oxide) layer with an intermediate silicon dioxide insulation layer, resulting in MOS-based architecture. The design optimization has been done using the SILVACO ATLAS-2D TCAD simulations by first calibrating the experimentally fabricated junctionless transistor. The study of the proposed gallium oxide gated junctionless phototransistor shows that the gallium oxide thickness of 30 nm is the best-optimized thickness with a maximum responsivity of 4.38 × 104 A/W and detectivity of 1.1 × 1012 Jones achieved at a very less required Vgs = −0.03 V. The spectral response has been performed and it has been calculated that the proposed architecture is best sensitive for 210 nm wavelength and sensitivity reduces significantly outside the deep UV solar spectrum. The time response analysis has also been presented, and it is concluded that the junctionless phototransistor has the advantage of less gate voltage requirements than other gallium oxide-based phototransistors with quite high responsivity in the deep UV solar spectrum.

Comparative analysis of junctionless and inversion-mode nanosheet FETs for self-heating effect mitigation

Artificial intelligence computing requires hardware like central processing units and graphic processing units for data processing. However, excessive heat generated during computations remains a challenge. The paper focuses on the heat issue in logic devices caused by transistor structures. To address the problem, the operational mechanism of the Junctionless Field-Effect Transistor (JLFET) is investigated. JLFET shows potential in mitigating heat-related issues and is compared to other nanosheet (ns) FETs. In the case of JL-nsFET, the change in mobility with increasing temperature is smaller compared to Con-nsFET, resulting in less susceptibility to lattice scattering and thermal resistance (Rth) in self-heating effect situation is 0.43 [K µW−1] for Con-nsFET and 0.414 [K µW−1] for JL-nsFET. The reason why the Rth of JL-nsFET is smaller than that of Con-nsFET is that JL-nsFET uses a source heat injection conduction mechanism and a large heat transfer area by using a bulk channel.

Synergic Effect of Misaligned Gate and Temperature on Hetero‐Dielectric Double‐Gate Junctionless Metal–Oxide‐Semiconductor Field‐Effect Transistors for High‐Frequency Application

Junctionless metal–oxide‐semiconductor field‐effect transistors (MOSFETs) have emerged as a promising alternative to conventional MOSFETs, offering simplified fabrication and potential performance improvements. The novelty of this research lies in the selection of hetero‐dielectric material to optimize the performance of junctionless transistors under the misaligned gate and high‐temperature conditions, and the aim is to explore its capability for low‐power high‐frequency application. The results reveal that the proposed junctionless field effect transistor exhibits increased transconductance (17 mS), which enables higher gain (311 dB) and diminishes capacitive effects, leading to a broader range of cutoff frequencies (154 GHz) with gain frequency product and gain transconductance frequency product are 31 and 95.9 THz, respectively. Moreover, this research article investigates critical reliability issues related to junctionless MOSFET, focusing on gate misalignment and thermal stability. The study reveals that gate misalignment reduces on‐current and degrades device performance. Additionally, the study examines thermal stability over a wide temperature range (300 to 500 K), exploring the impact of temperature on performance. These valuable findings provide crucial insights to overcome fabrication challenges and drive the practical adoption of junctionless MOSFETs in future integrated circuits. To assess device performance in high‐frequency applications, Silvaco ATLAS TCAD tools are employed.

Impacts of Cavity Thickness and Insulating Material on Dielectric Modulated Trench Junction-less Double Gate Field Effect Transistor for Biosensing Applications

Introduction: This work represents the influence of gate dielectric, and the nano-cavity gap of a dielectric modulated trench gate Junction-less Double Gate Field Effect Transistor (JL-DGFET) on the different performance indicators is investigated considering the Low-Frequency Noise. Methods:: It is noted that the gate dielectric and the nanogap, both parameters, have a substantial influence on the sensing capacity and performance of noise of the device. Results:: A double gate suitable dielectric material and cavity thickness can effectively improve the biosensor’s sensitivity with a minimum amount of noise. Conclusion:: The sensitivity is found to increase up to 9.5 for dielectric constant, k = 3.57 and 6.5 for dielectric constant, k = 2.1.

Germanium- and Silicon-Nanotransistor Designs by Electrical and Thermal Self-Consistent Analysis

This study evaluated nanometer gate length germanium (Ge) transistors, including the electrical and thermal components, and compared them with silicon (Si) transistors. Nanometer-scale Ge and Si junction-less field-effect transistors (JLFETs) were treated for both NFET and PFET devices under a transient response. Consequently, the electrical and thermal self-consistent simulations revealed that hole carrier transport is more challenging at the channel region for PFET, inhibiting process shrinking. Moreover, the results show that self-heating can reach a dangerous stature, particularly when the channel region is thick. This is because the operation of the nanometer-scale Ge and Si JLFETs depends on the quantum effect, which increases the band-gap energy. The suitable channel design for Ge and Si transistors is almost similar; a heavier doping concentration is favorable for Si transistors. The study concludes that optimizing the channel region to fit the band-gap energy is the most crucial aspect for designing transistors.

An analytical model for P+ pocket SiC gate all around Junctionless field effect transistor with impact of high temperature

In this article, we examined the influence of temperature in P+ pocket silicon carbide (SiC) gate all around junctionless field effect transistor (GAA JLFET). The inclusion of P+ pocket on source and drain side regions lead to an efficient volume depletion in JLFET. This results in increased tunneling width at channel-drain interface which reduced the L-BTBT induced OFF-state current of order to ∼10−15. It has been observed that using wide band gap material SiC as nanowire make the device temperature immune at higher drain voltages. A compact model with consideration of Poisson's equation for nanowire has been developed for surface potential (φi (r, z, T)), threshold voltage (Vth) and electric field (Ez) for P+ pocket SiC GAA JLFET. The P+ pocket has been considered while modeling the surface potential and electric field of SiC GAA JLFET. The presented compact model include the influence of temperature on surface potential and electric field as well. The performance of proposed compact model has been further validated with simulations results obtained from the SILVACO TCAD and it has shown the good agreement with simulation results.

Performance Analysis of Multi-Channel-Multi-Gate-Based Junctionless Field Effect Transistor

In this paper, a multi-gate junctionless field-effect transistor with a quad gate and multiple channels has been proposed and thoroughly simulated. The proposed device offers a lower I off current of 4.34 × 10−19 A, an I on current of 4.17 × 10−06 A with an I on/I off current ratio of 9.65 × 1012, a threshold voltage of 0.86 V, a transconductance of 5 × 10−05 S, a drain-induced barrier lowering (DIBL) of 22 mV/V, and a subthreshold slope (SS) of 61.51 mV/dec. The visual contour plots of the device are also included in this study to understand the working mechanism. The larger tunneling width between the channel drain and barrier height between the source–channel interface exhibits a lower leakage current and better performance. The performance of the proposed device is also studied when the work function between the semiconductor and gate material is altered. The work function difference improves the performance metrics. Aside from that, the effects of temperature variation on the device's performance characteristics are also being studied. When the temperature varies by 33% the threshold voltage of the proposed device drops by only 7% which shows a minimum variation in the proposed device. The results obtained from the proposed device exhibit the potential of using multi-gate multi-channel junctionless field effect transistor (MCMG) device in low-power logic circuits and memory devices.

Comprehensive study of gate induced drain leakage in nanowire and nanotube junctionless FETs using Si1-xGex source/drain

We present, in this paper, optimized nanotube (NT) and nanowire (NW) junctionless field-effect transistor (JLFET) architectures of gate-induced drain leakage (GIDL). At the source/ drain–channel interface, SiGe creates a valence energy band discontinuity which alleviates lateral band-to-band tunneling (L-BTBT) of electrons in the OFF-state. It is established through 2-D TCAD simulations that inclusion of SiGe decreases L-BTBT in the NTJLFET by >5 orders, thus leading to a substantial ION/IOFF of with precision 1012 for a 20 nm gate length which is not attainable in the conventional NTJLFET (ION/IOFF ∼ 106). Furthermore, degraded OFF-state current in NWJLFET because of conventional charge-sharing effect improves with the inclusion of SiGe by ∼2 orders of magnitude. Additionally, it is effective to place SiGe layers positioned at the source and drain regions and SiGe/ Si interface inside or at the channel region. Based on the proposed design guidelines, we show that the optimized SiGe S/D NTJLFET is effective in reduction of L-BTBT GIDL when gate length is scaled to 5 nm.

Investigation of Gate Induced Drain Leakage in Nanotube and Nanowire: A Comprehensive Study

In this paper, a comprehensive study of gate-induced drain leakage (GIDL) in conventional silicon-nanotube (Si-NT JLFET), SiGe Source/Drain silicon-nanotube junctionless field effect transistor (S/D Si-NT JLFET) and conventional nanowire (NW) have been performed using technology computer-aided design simulations. We have also demonstrated that inclusion of SiGe S/D in Si-NT JLFET reduced the OFF-state current by order of [Formula: see text]3 from NT JLFET and by order of [Formula: see text]6 from NW JLFET. The impact of variation of core gate thickness ([Formula: see text], germanium (Ge) content [Formula: see text], and location of SiGe in source and drain regions of the S/D Si-NT JLFET have been studied from the GIDL perspective. We found that SiGe S/D Si-NT JLFET exhibits impressively high [Formula: see text]/[Formula: see text] ratio [Formula: see text]10[Formula: see text] with reduced lateral band-to-band tunneling (L-BTBT)-induced GIDL than the conventional nanowire device. The is due to SiGe S/D that creates a energy valence band discontinuity at source drain interfaces which limits the flow of electrons from channel to drain region in the OFF-state.

Performance analysis of short channel effects immune JLFET with enhanced drive current

AbstractThis manuscript reports analog/RF and noise analysis of a novel junctionless field effect transistor. To reduce the gate induced drain leakage (GIDL), step‐gate‐oxide structure is used with a high‐k buried oxide (BOX) which subsequently reduces IOFF. The off current and gate capacitance is reduced by including step‐gate‐oxide in high k‐BOX JLFET due to increase in the band to band tunneling (BTBT) width. The DIBL is reduced significantly to 0.014 which is 60% less as compared to high‐k BOX JLFET (HB JLFET). For different length and thickness of the step‐gate‐oxide, the analog/RF and noise performance of the step‐gate‐oxide JLFET with high‐k BOX (SGO HB JLFET) have also been investigated in detail. Silvaco TCAD simulation of the proposed structure for 20 nm channel length shows an extremely high ION/IOFF ratio of ~108. The subthreshold swing for the simulated structure was also found to be considerably low (82 mV/dec).