Junction Termination Extension Research Articles

2D Electric field imagery in 4H-SiC power diodes using OBIC technique

Wide band gap semiconductors are more and more used, especially to design high voltage devices. However, some devices show lower breakdown voltages than those predicted in theory. These early breakdown are in general due to imperfections in the peripheral protections of the active junction. The aim of these protections is to reduce electric field peaks at the periphery of the junction. Thus, it is important to study the electric field distribution on the device periphery to detect any protection weakness. This paper presents a 2D electric field imagery using OBIC (optical beam induced current) technique. 2D cartographies are realized on JTE (junction termination extension) protected diodes in order to display electric field on diode peripheries. Other measurements are also performed on circular avalanche diodes protected with a MESA etching and provided with optical window. In both cases, OBIC techniques is demonstrated to be an efficient method to obtain electric field distribution within the device and to locate defects.

Analytical Model and New Structure of the Variable-<inline-formula> <tex-math notation="LaTeX">$k$ </tex-math></inline-formula> Dielectric Trench LDMOS With Improved Breakdown Voltage and Specific ON-Resistance

A novel Silicon-on-Insulator laterally double-diffused metal-oxide-semiconductor transistor with ultralow specific ON-resistance ( $R_{\mathrm{{\scriptscriptstyle ON}},{\mathrm{ sp}}})$ is proposed, and its analytical model for the breakdown voltage (BV) is presented. The device features a variable- ${k}$ dielectric trench and a p-pillar beside the trench (VK-P). First, the VK trench induces additional field peaks and thus significantly increases the average electric field (E-field) strength. Second, the low- $k$ dielectric in the upper trench leads to a high E-field strength, enabling a shortened device pitch to support the high BV. Third, the p-pillar extending from the p-body to the trench bottom not only acts as the vertical junction termination extension, but also forms the enhanced vertical reduced surface field effect, which further modulates the E-field distribution and increases the drift doping concentration. The BV and $R_{\mathrm{{\scriptscriptstyle ON}},{\mathrm{ sp}}}$ are, therefore, greatly improved. At 600 V class BV, the VK-P LDMOS reduces the $R_{\mathrm{{\scriptscriptstyle ON}},{\mathrm{ sp}}}$ by 54% compared with the uniform- $k$ trench LDMOS. An analytical BV model taking account of influence of the VK dielectric trench is presented for the first time. The analytical results agree well with the simulated results.

(Invited) Vertical GaN p-i-n Diodes Formed by Mg Ion Implantation

GaN is an ideal material for power applications due to its high breakdown field, high switching speed, and low switching losses. The ability to implant and activate dopants, particularly p-type dopants, in GaN still remains a challenge. Dopant implantation and activation is crucial for many devices since it is the most straightforward method of selective lateral doping in GaN. Devices such as the current aperture vertical electron transistor (CAVET), Schottky diodes with guard ring termination or grayscale junction termination extension, and vertical p-i-n diodes will be enhanced and enabled by the ability to selectively dope GaN without the need for etching or regrowth. Herein, we report on the first implanted p-i-n diode fabricated on a bulk GaN substrate. A 8 μm thick unintentionally doped GaN layer was grown by metal organic chemical vapor deposition (MOCVD) on a n+ Ga-face c-oriented GaN substrate. The p-GaN anode and termination regions were formed by Mg implantation to a concentration of 2x1019 cm-3 following a box profile to a depth of 500nm. The implanted dopants were activated using the multicycle rapid thermal annealing (MRTA) technique described elsewhere [1]. After activation and removal of the protective cap structure [2], a 1 μm SiO2 field oxide layer was deposited by plasma enhanced chemical vapor deposition (PECVD). Contact windows were opened by reactive ion etching in a CHF3-based plasma. The anode metal was formed by lift-off of Pd/Au (20/100nm), followed by rapid thermal annealing in a N2atmosphere, and the cathode metal was a blanket film of e-beam deposited Al on the back side of the sample. Rectifying behavior was observed, a first for a p-i-n structure formed by Mg ion implantation in GaN. The turn-on voltage is consistent with a p-n junction, and the ideality factor of 2.6 is consistent with a recombination/generation-based transport mechanism, confirmed by temperature-dependent I-V. Additional non-ideal behavior is associated with recombination in the drift layer due to crystalline defects. The devices suffer from high ON-resistance due to high contact resistance and recombination in the drift layer, which limited the forward current to 1 A/cm2. Capacitance-voltage measurements indicated the presence of a p-GaN layer, with a depletion layer thickness ~500nm and a doping density of 2x1018 cm-3, corresponding to an activation ratio of 10%. 1. B.N. Feigelson, et. al. J. Cryst. Growth. 350, 21-26 (2012) 2. J.D. Greenlee, et. al. Appl. Phys. Express 8 036501 (2015)

Experimental Study of Counter-Doped Junction Termination Extension for 4H–SiC Power Devices

In this letter, a counter-doped junction termination extension (CD-JTE) structure was experimentally implemented and studied. Two groups of 4H-SiC PiN diodes were fabricated with two n-type drift layer thicknesses of 11 and 30 μm, respectively, and with different termination structures, in order to demonstrate the wide JTE dose tolerance of CD-JTE. Three different doses, 1.7 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">13</sup> , 2.2×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">13</sup> , and 2.8×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">13</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> , were used for the critical JTE implantation. The measured breakdown voltages (BVs) of the diodes with all termination structures and JTE doses were compared with simulation predictions. Electroluminescence at the BV was recorded and used to locate the peak electrical field. The test results matched well with the simulation results. As a result of the effectiveness and robustness of the CD-JTE, the best achieved BVs from the diodes on the 11and 30-μm epilayers were 1850 and 4800 V, respectively.

Investigation of the Breakdown Voltage in High Voltage 4H-SiC BJT with Respect to Oxide and Interface Charges

Ion implantation in silicon carbide (SiC) induces defects during the process. Implantation free processing can eliminate these problems. The junction termination extension (JTE) can also be formed without ion implantation in SiC bipolar junction transistor (BJT) using a well-controlled etching into the epitaxial base layer. The fixed charges at the SiC/SiO2 interface modify the effective dose of the JTEs, leakage current, and breakdown voltage. In this paper the influence of fixed charges (positive and negative) and also interface trap density at the SiC/SiO2 interface on the breakdown voltage in 4.5 kV 4H-SiC non-ion implanted BJT have been simulated. SiO2 as a surface passivation layer including interface traps and fixed charges has been considered in the analysis. Simulation result shows that the fixed charges influence the breakdown voltage significantly more than the interface traps. It also shows that the positive fixed charges reduce the breakdown voltage more than the negative fixed charges. The combination of interface traps and fixed charges must be considered when optimizing the breakdown voltage.

The Impact of Interface Charge on the Breakdown Voltage of Terminated 4H-SiC Power Devices

A novel method for analyzing a decrease in breakdown voltage (VBD) in the termination of 4H-SiC power devices after reverse-bias stressing on the basis of change in depletion-layer capacitance is proposed. Test PN diodes terminated with a junction-termination extension (JTE) were fabricated on n-type 4H-SiC and analyzed by I-V and C-V measurements. According to the results of the measurements, VBD after stressing decreases, and the capacitance of the test devices decreases after stressing. Measurements with different chip sizes but the same termination width show that the capacitance decrease occurs in the termination area. The simulated capacitance change, on the supposition that positive charge accumulated at the SiO2/SiC interface, and the measured capacitance change show the same tendency. These results indicate that the origin of VBD decrease is positive charge accumulated at the SiO2/SiC interface of the termination after reverse-bias stressing.

Robust Double-Ring Junction Termination Extension Design for High Voltage Power Semiconductor Devices Based on 4H-SiC

In this study, a new robust double-ring junction-termination-extension (DR-JTE) for high-voltage pn-diodes is presented and analyzed using numerical simulations. As figured out, the DR-JTE reduces the electrical field at both, the edge of the single-JTE region and the MESA-transition, respectively. Thereby, due to the reduction of the electrical field, the maximum breakdown voltage is increased to 91.5% of the theoretical, parallel-plane breakdown voltage of 6.5kVand the maximum acceptable deviation of the optimum implantations dose is twice than that of the single-JTE structure. Furthermore, due to the internal ring, the MESA-transition is shielded from the electrical field and therefore the breakdown voltage is much less affected by the angle of the MESA.

4.5-kV 20-mΩ.cm&lt;sup&gt;2&lt;/sup&gt; Implantation-Free 4H-SiC BJT with Trench Structures on the Junction Termination Extension

A single-mask junction termination extension withtrench structures is formed to realize a 4.5 kV implantation-free 4H-SiCbipolar junction transistor (BJT). The trench structures are formed on the baselayer with dry etching using a single mask. The electric field distributionalong the structure is controlled by the number and dimensions of the trenches.The electric field is distributed by the trench structures and thus the electricfield crowding at the base and mesa edges is diminished. The design isoptimized in terms of the depth, width, spacing, and number of the trenches toachieve a breakdown voltage (VB) of 4.5 kV, which is 85% of thetheoretical value. Higher efficiency is obtainable with finer lithographicresolution leading to smaller pitch, and higher number and narrower trenches.The specific on-resistance (RON) of 20 mΩ.cm2 is measuredfor the small-area BJT with active area of 0.04 mm2. The BV-RONof the fabricated device is very close to the SiC limit and by far exceeds thebest SiC MOSFETs.

Bevel Junction Termination Extension—A New Edge Termination Technique for 4H-SiC High-Voltage Devices

A new edge termination method, referred to as a bevel junction termination extension (Bevel-JTE), is presented for high-voltage silicon carbide devices. The 4H-SiC PiN rectifiers, with a breakdown voltage of 1600 V ( $\sim 95$ % of the theoretical value), were fabricated using Bevel-JTEs. The Bevel-JTE technique significantly reduces the chip size by decreasing space occupied by edge termination while providing broad process latitude for parameter variations, such as implantation dose and activation anneal condition.

Development of high-resolution silicon-based particle sensor with integrated amplification

The electronic noise of the front-end preamplifier can potentially limit the energy and position resolutions of radiation sensors, a detrimental effect that can be diminished by the use of on-chip amplification. The implementation of an avalanching structure upon a direct-conversion semiconductor-based radiation detector is modeled and demonstrated using high-resistivity silicon. The avalanche particle sensor configuration is designed analytically, and we validated the design with numerical process and device simulations. Process and device simulation results from the sensors modeled with various geometries, doping profile arrangements, and fabrication conditions are reported. We tested the refined numerical design by fabricating and testing diagnostic sensors. Multiplication junctions, based on a junction termination extension design, were created from micrometer-scale highly-doped layers on silicon wafers using both diffusion and ion implantation techniques. For <100keV energy depositions, our modeling has shown that a gain of ~8 is ideal if one is attempting to optimize the SNR, which is realized in the experimental detectors at an excess bias of 3V. At that voltage, the energy resolution for 81keV gamma-rays can, in principle, be reduced from 2.12% to 0.96% (for a kα=0.2 device), the degree of improvement limited by the leakage current of the devices, and within a factor of 2 of the ultimate Fano limit (0.53%).

Counter-Doped JTE, an Edge Termination for HV SiC Devices With Increased Tolerance to the Surface Charge

In this paper, a comparison of different techniques for SiC high-voltage devices is performed using numerical simulations. In particular, the method of counter doping (CD) introduced in the junction termination extension (JTE) region to create a multizone termination effect is investigated. Simulation shows that compared with the other edge termination techniques, CD-JTE greatly reduces the sensitivity of breakdown voltage (BV) to JTE doses and surface charges. The multizone CD-JTE with outer rings shows that for a 30-μm thick epi-layer, 90% of the theoretical BV is achievable with a wide tolerance of 11 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> /cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> to the JTE dose and 85% of the theoretical BV with an increased tolerance of 6.19 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> /cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> to the positive surface charges, both superior to other JTE structures investigated in this paper.

Ultralow specific on-resistance high voltage trench SOI LDMOS with enhanced RESURF effect

A RESURF-enhanced high voltage SOI LDMOS (ER-LDMOS) with an ultralow specific on-resistance (Ron, sp) is proposed. The device features an oxide trench in the drift region, a P-pillar at the sidewall of the trench, and a buried P-layer (BPL) under the trench. First, the P-pillar adjacent to the P-body not only acts as a vertical junction termination extension (JTE), but also forms a vertical reduced surface field (RESURF) structure with the N-drift region. Both of them optimize the bulk electric field distributions and increase the doping concentration of the drift region. Second, the BPL together with the N-drift region and the buried oxide layer (BOX) exhibits a triple-RESURF effect, which further improves the bulk field distributions and the doping concentration. Additionally, multiple-directional depletion is induced owing to the P-pillar, the BPL, and two MIS-like structures consisting of the N-drift region combined with the oxide trench and the BOX. As a result, a significantly enhanced-RESURF effect is achieved, leading to a high breakdown voltage (BV) and a low Ron, sp. Moreover, the oxide trench folds the drift region in the vertical direction, resulting in a reduced cell pitch and thus Ron, sp. Simulated results show that the ER-LDMOS improves BV by 67% and reduces Ron, sp by 91% compared with the conventional trench LDMOS at the same cell pitch.

Novel Designed SiC Devices for High Power and High Efficiency Systems

Two types of 4H-silicon carbide (SiC) MOSFETs are proposed in this paper. One is the novel designed V-groove trench MOSFET that utilizes the 4H-SiC (0-33-8) face for the channel region. The MOS interface using this face shows the extremely low interface state density (Dit) of 3 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> eV <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> , which causes the high channel mobility of 80 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> s <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> results in very low channel resistance. The buried p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> regions located close to the trench bottom can effectively alleviate the electric field crowding without the significant sacrifice of the increase of the resistance. The low specific ON-state resistance of 3.5 mQ cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with sufficiently high blocking voltage of 1700 V is obtained. The other is the double implanted MOSFET with the carefully designed junction termination extension and field-limiting rings for the edge termination region, and the additional doping into the junction FET region. With a high-quality and high-uniformity epitaxial layer, 6 mm × 6 mm devices are fabricated. The well balanced specific ON-state resistance of 14.2 mQ cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and the blocking voltage of 3850 V are obtained for 3300 V application.

Ultrahigh-Voltage SiC p-i-n Diodes With Improved Forward Characteristics

Silicon carbide (SiC) p-i-n diodes having five different n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> -layer (i-layer) thicknesses from 48 to 268 μm are fabricated. The forward characteristics of SiC p-i-n diodes are significantly improved by carrier-lifetime enhancement. After this improvement, the differential on-resistance is inversely proportional to the square root of current density for all the diodes with different thicknesses of n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> -layer. As a result, the forward current density-voltage characteristics can be approximately expressed by a parabolic function, as in the case of Si p-i-n diodes. Using a 268-μm-thick n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> -layer, the lifetime enhancement, and an improved space-modulated junction termination extension structure, a very high blocking voltage over 26.9 kV and low differential on-resistance of 9.7 mΩ·cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> are achieved.

5.8-kV Implantation-Free 4H-SiC BJT With Multiple-Shallow-Trench Junction Termination Extension

Implantation-free 4H-SiC bipolar junction transistors with multiple-shallow-trench junction termination extension have been fabricated. The maximum current gain of 40 at a current density of 370 A/ $\mathrm{cm}^{2}$ is obtained for the device with an active area of 0.065 $\mathrm{mm}^{2}$ . A maximum open-base breakdown voltage (BV) of 5.85 kV is measured, which is 93% of the theoretical BV. A specific on-resistance ( $R_{\mathrm{{\scriptstyle ON}}}$ ) of 28 m $\Omega \cdot {\rm cm^{2}}$ was obtained.

Characterization of deep electron traps in 4H-SiC Junction Barrier Schottky rectifiers

Conventional deep level transient spectroscopy (DLTS) technique was used to study deep electron traps in 4H-SiC Junction Barrier Schottky (JBS) rectifiers. 4H-SiC epitaxial layers, doped with nitrogen and grown on standard n+−4H-SiC substrates were exposed to low-dose aluminum ion implantation process under the Schottky contact in order to form both JBS grid and junction termination extension (JTE), and assure good rectifying properties of the diodes. Several deep electron traps were revealed and attributed to impurities or intrinsic defects in 4H-SiC epitaxial layers, on the basis of comparison of their electrical parameters (i.e. activation energies, apparent capture cross sections and concentrations) with previously published results.

4H-SiC Diode Avalanche Breakdown Voltage Estimation by Simulation and Junction Termination Extension Analysis

This paper presents and compares different avalanche breakdown voltage estimation methods in 4H-SiC (silicon carbide) using finite element simulation results on Schottky diode. 4H-SiC avalanche breakdown voltage and depletion width estimated with Baligas equations have shown to be higher than other estimation techniques and simulation results, especially for voltages higher than 5kV. This paper discusses the impact of choosing different junction termination extension (JTE) structures on two-dimensional junction curvature effects and electric field crowding for Schottky diodes Space-Modulated JTE (SMJTE) structure with optimum JTE dose and dimension could achieve up to 90% of the parallel plane breakdown voltage. For ultra high voltage devices (&gt;15 kV) the SMJTE has significant improvement in terms of breakdown voltage. It also has a wider optimum JTE dose window. For 1 kV device there is not a significant difference in breakdown voltage between JTE and SMJTE structures.

Ultrahigh-Voltage (&gt; 20 kV) SiC PiN Diodes with a Space-Modulated JTE and Lifetime Enhancement Process via Thermal Oxidation

Ultrahigh-voltage SiC PiN diodes with an original junction termination extension (JTE) structure and improved forward characteristics are presented. A space-modulated JTE (SM-JTE) structure was designed by device simulation, and a high breakdown voltage of 26.9 kV was achieved by using a 270 μm-thick epilayer and 1050 μm-long JTE. In addition, lifetime enhancement process via thermal oxidation was performed to improve the forward characteristics. The on-resistance of the SiC PiN diodes was remarkably reduced by lifetime enhancement process. The temperature dependence of the on-resistance was also discussed.

Study of 4H-SiC Schottky Diode Designs for 3.3kV Applications

The static performance of different active and termination area designs for SiC-based Schottky diodes, suitable for 3.3kV applications, were investigated by means of extensive numerical simulations. We found quantitatively that the high electric field of SiC close to avalanche-breakdown is shielded most effectively from the Schottky interface by a trench-based design. Moreover, we conclude that the edge termination design with junction termination extension and four implanted p+ guard rings is most robust against oxide interfacial charge.

Blocking Characteristics of 2.2 kV and 3.3 kV-Class 4H-SiC MOSFETs with Improved Doping Control for Edge Termination

Blocking characteristics of 2.2 kV and 3.3 kV -class 4H-SiC MOSFETs with various doping conditions for the edge termination region have been investigated. By optimizing the implanted dose into the edge termination structure consisting of junction termination extension (JTE) and field limiting ring (FLR), a breakdown voltage of 3,850 V for 3.3 kV -class MOSFET has been attained. This result corresponds to about 95% of the approximate parallel-plane breakdown voltage estimated from the doping concentration and the thickness of the epitaxial layer. Implanted doping for the JFET region is effective in reducing JFET resistance, resulting in the specific on-resistance of 14.2 mΩcm2 for 3.3 kV SiC MOSFETs. Switching characteristics at the high drain voltage of 2.0 kV are also discussed.