Chip Junction Temperature Research Articles

Finite Element Analysis of LED Heat Dissipation Performance Based on Graphene Composites

Abstract With the gradual development of integrated circuits to thin, high-performance and versatile of electronic products is becoming more and more powerful, and its integration and assembly density continue to improve, which will lead to the increase of its working power consumption and heat. If not timely treatment of heat dissipation problems, which will lead to heat concentration in the diode PN junction, it will reduce the service life of LED lights, and in severe cases, it will even burn the LED device. Therefore, it is crucial to improve heat dissipation efficiency of LED and reduce the junction temperature of chip. An LED structure with aluminum material and an LED structure with graphene material are analyzed by finite element method to study the heat dissipation efficiency of the graphene material. The results reveal that the heat dissipation effect of high conductivity graphene composites provides a convenient evaluation method for the subsequent use of the new materials. The research in this paper shows that the software simulation method can effectively analyze the thermal conductivity of practical engineering applications.

Online Recognition of Fallen-Off Bond Wires in IGBT Modules.

As a core component of power conversion systems, insulated gate bipolar transistor (IGBT) modules continually suffer from severe thermal damage caused by temperature swings and shear stress, resulting in fatigue failure. Bond wires falling off is one of the failure modes of IGBT modules. Given that the number of fallen-off bond wires is a significant parameter to evaluate the health status of the IGBT modules, this paper proposes an online identification model to recognize the number of fallen-off bond wires during normal operation. Firstly, a database containing datum Vce,on-Tj-IC (collector-emitter on-state voltage Vce,on, chip junction temperature Tj, collector current IC) planes with different fallen-off bond wires is built based on an offline aging test. Secondly, a Foster network model and a special circuit are designed to measure the junction temperature Tj and the collector-emitter on-state voltage Vce,on, respectively. Thirdly, the feature points of the IGBT module represented by Vce,on, Tj, and IC are given to the database to recognize the number of fallen-off bond wires according to the position of the feature points in the datum plane. The experimental results show that the proposed method can determine the fallen-off bond wires under the operation condition.

Power-cycling degradation monitoring of an IGBT module with VCE(sat) measurement in continuous operation of a chopper circuit

This paper presents a power-cycling degradation monitoring method of an IGBT module with a VCE(sat) sensing circuit and junction temperature prediction by a three-dimensional structure model. A chopper circuit was introduced to provide a continuous-current-conducting operation of the IGBT module. The VCE(sat) sensing circuit with a low-cost IoT platform “Leafony” was utilized to monitor the junction temperature of an IGBT chip, which transferred the measured signal as digital data, and thus obtained a higher noise immunity than an analog-based circuit. The junction temperature of IGBT chip in the power module was analyzed from the dissipated power of IGBT and the transient thermal impedance between the chips and the ambient. This analysis is effective not only to observe the degradation but also to estimate the thermal resistance. Comparing the temperature profile between experiment and prediction provides health condition of the IGBT model.Predicted thermal profiles agreed with measured ones with 10 % increase of thermal resistance, which was degraded by a power cycle tester. From these results, the proposed monitoring method is effective to detect the progress of power cycle degradation.

High Thermal Performance Ultraviolet (368 nm) AlGaN-Based Flip-Chip LEDs with an Optimized Structure

In this study, we have fabricated a 368 nm LED with an epitaxial Indium Tin Oxide (ITO) contact layer. We analyze the thermal performance of the flip-chip LED with a symmetric electrode and metal reflective layer, applying ANSYS to build a coupled electro-thermal finite element model (FEM) of the temperature distribution in the multiple quantum wells (MQWs). We compare our system with the traditional Au-bump flip-chip LED and a flip-chip LED with a Distributed Bragg Reflector (DBR) layer. The simulation results have shown that the flip-chip LED with a metal reflective layer and symmetric electrode exhibits better heat dissipation performance, particularly at high input power. The influence of the insulating layer on the LED chip junction temperature is also examined. The simulation data establish an effect due to the thermal conductivity of the insulating layer in terms of heat dissipation, but this effect is negligible at an insulation layer thickness ≤1 µm.

Forced boiling of nonazeotropic immiscible mixture in a supercapillary microchannel array for ultra-high heat flux removal with chip junction temperature below 85°C

Forced boiling of nonazeotropic immiscible mixture in a supercapillary microchannel array for ultra-high heat flux removal with chip junction temperature below 85°C

Optimization of Package Heat Dissipation Design Based on High-power WB-BGA Industrial Chip with a Wide Temperature Range

With the progress of science and technology, chip integration and packaging density continue to improve, and the power density increases rapidly, leading to the increasingly prominent problem of chip heat dissipation. The service environment of industrial chips with a wide temperature range is even worse, so it is necessary to ensure reliable operation in the environment of −40°C~85°C. The thermal design and thermal management of packaging have become an important problem in the industry. Based on the wide temperature range of high-power WB-BGA industrial chips, aiming at the difficulty of chip heat dissipation in the high-temperature environment of 85°C, this paper studies and optimizes the packaging heat dissipation, and proposes a high heat dissipation packaging design scheme based on the wide temperature-range high-power WB-BGA industrial chip, which reduces the chip junction temperature by 17.9°C and has a certain reference value for the packaging design of wide temperature range industrial chip.

Ground-facing radiative cooling for high power LED lights

Objects on Earth facing the sky have the ability to emit thermal energy into the universe through the transparent atmosphere. This process can enable electricity-free cooling due to the extremely low temperature of outer space. However, factors such as humidity, clouds, and air pollution within the atmosphere can affect this process, particularly for electricity-free sub-ambient cooling applications. For high-temperature objects, the dependency of radiative cooling performance on the environment is significantly reduced. In this study, we explore the potential of utilizing ground-facing radiative cooling for improved high-power light-emitting-diode (LED) lighting applications. By using a transparent material, like polyethylene, as the front cover of the LED light package, one can efficiently release thermal radiation from the semiconductor chips that can reach temperatures of 60–130 °C. As a result, we demonstrate a reduction in the operational temperature of the LED chip by 3.9 °C in controlled indoor settings and by 3.7 °C in selected outdoor environments. Our analysis reveals that employing ground-facing radiative cooling can enhance the luminous efficacy of LED lights by approximately 3.0%. Assuming all current global electricity consumption is used for LED lights, this enhancement translates to an estimated annual energy savings of 128 terawatt-hours and a reduction in carbon dioxide emissions by 55 million metric tons. Remarkably, according to our aging experiment over 4000 h, this method can extend the lifespan of LED lights by 21.7% due to the lowered junction temperature of the semiconductor chip, resulting in reduced material, labor, and maintenance costs for future global LED lighting products.

Thermal Performance Optimization of Integrated Microchannel Cooling Plate for IGBT Power Module.

In high-integration electronic components, the insulated-gate bipolar transistor (IGBT) power module has a high working temperature, which requires reasonable thermal analysis and a cooling process to improve the reliability of the IGBT module. This paper presents an investigation into the heat dissipation of the integrated microchannel cooling plate in the silicon carbide IGBT power module and reports the impact of the BL series micropump on the efficiency of the cooling plate. The IGBT power module was first simplified as an equivalent-mass block with a mass of 62.64 g, a volume of 15.27 cm3, a density of 4.10 g/cm3, and a specific heat capacity of 512.53 J/(kg·K), through an equivalent method. Then, the thermal performance of the microchannel cooling plate with a main channel and a secondary channel was analyzed and the design of experiment (DOE) method was used to provide three factors and three levels of orthogonal simulation experiments. The three factors included microchannel width, number of secondary inlets, and inlet diameter. The results show that the microchannel cooling plate significantly reduces the temperature of IGBT chips and, as the microchannel width, number of secondary inlets, and inlet diameter increase, the junction temperature of chips gradually decreases. The optimal structure of the cooling plate is a microchannel width of 0.58 mm, 13 secondary inlets, and an inlet diameter of 3.8 mm, and the chip-junction temperature of this structure is decreased from 677 °C to 77.7 °C. In addition, the BL series micropump was connected to the inlet of the cooling plate and the thermal performance of the microchannel cooling plate with a micropump was analyzed. The micropump increases the frictional resistance of fluid flow, resulting in an increase in chip-junction temperature to 110 °C. This work demonstrates the impact of micropumps on the heat dissipation of cooling plates and provides a foundation for the design of cooling plates for IGBT power modules.

A dumbbell-shaped 3D flat plate pulsating heat pipe module augmented by capillarity gradient for high-power server CPU onsite cooling

With the development of the data center industry and the increasing power density of servers, it is crucial to remove waste heat from small-area heat sources to ensure the safe and efficient operation of data processing chips. To complement existing studies, in this paper, a novel three-dimensional flat plate aluminum pulsating heat pipe (3D-FPPHP) with four different channel structures for radial heat dissipation of high-power server chips was proposed. The results showed that under the favorable influence of the additional capillarity force provided by the variable diameter channels, the FPPHP filled with acetone can start up easily and has good robustness during variable power operation. When the input power was 150 W, the junction temperature of the heating source could be reduced by 42.49 °C (48.67%) compared to an identical aluminum plate. In addition, a heat sink module based on the proposed 3D-FPPHP with optimal charging ratio was tested in a 1U server chassis. The results showed that it can manage an input power of 300 W (corresponding to a heat flux of 41.15 W/cm2) and achieve a total thermal resistance of 0.2053 °C/W under the premise of ensuring a safe junction temperature of chips below 85 °C.

Structure optimization, optical design and thermal management of UVC LED photoreactor to improve its inactivation efficiency

Compared with the chlorine disinfection, ultraviolet light emitting diode (UV LED) has attracted extensive interest due to its advantages of environmental friendliness, wide inactivation range and easy automation. However, there are still some challenges on how to apply UV LED to water disinfection more effectively by designing and optimizing some parameters. In this manuscript, the optimal numbers, spacing and configuration of UVC LEDs are systematically studied using the thermal and optical software simulation and experiment methods. Then, the influence of the reactor shape and reflective material on inactivation efficiency of the photoreactor was studied in detail. The results show that the appropriate numbers and spacing of UVC LEDs is helpful not only to increase the average irradiance and petri factor of reactor surface but also to keep a low chip junction temperature. The simulation results of three UVC LED configurations indicate the four corners configuration exhibits the highest average irradiance and petri factor value. The introduction of reflective materials can enhance the inactivation performance, and especially the polytetrafluoroethylene (PTFE) material can effectively increase the inactivation efficiency of module by ∼42% because of higher reflectivity and light uniformity. The further inactivation experiments reveal that the designed cylinder reactor covered with PTFE materials has the maximum log inactivation value. The current research results can provide some reliable suggestions for the design and optimization of UVC LED photoreactor to improve its inactivation effect through optical simulation and experimental methods.

Comparative Study of the Parameter Acquisition Methods for the Cauer Thermal Network Model of an IGBT Module

Under the operating conditions of high power and high switching frequency, an insulated gate bipolar transistor (IGBT) chip can produce relatively large power loss, causing the junction temperature to rise rapidly; consequently, the reliability of the IGBT module can be seriously affected. Therefore, it is necessary to accurately predict the junction temperature of the IGBT chip. The resistance capacitance (RC) thermal network model is a commonly used method for IGBT junction temperature prediction. In this paper, the model parameters are obtained by two methods to establish the Cauer thermal network models of the IGBT module. The first method is to experimentally obtain the transient thermal impedance curve of the IGBT module and the structure function and then extract the individual thermal parameters of the Cauer thermal network model; the second method is to obtain the thermal parameters of the thermal network model directly by using theoretical formulas that consider the influence of the heat spreading angle. The predicted junction temperatures of the Cauer thermal network models established by the two methods are compared with the junction temperatures obtained from infrared (IR) measurements during the power cycling test, the junction temperatures measured by the temperature-sensitive electrical parameter (TSEP) method, and the junction temperatures calculated by finite element (FE) analysis. Additionally, the Cauer thermal network models established by the two methods are compared and verified. The results indicate that the Cauer thermal network model established based on theoretical formulas can accurately predict the maximum junction temperature of the IGBT chip, and the calculated temperature for each layer, from the IGBT chip layer to the ceramic layer, also accords well with the FE results. The Cauer thermal network model established based on the experimental test and the structure function can accurately predict the average junction temperature of the IGBT chip.

MULTI-CHIP COUPLING THERMAL RESISTANCE TOPOLOGICAL NETWORK MODEL AND CHIP JUNCTION TEMPERATURE PREDICTION OF SYSTEM IN PACKAGE

MULTI-CHIP COUPLING THERMAL RESISTANCE TOPOLOGICAL NETWORK MODEL AND CHIP JUNCTION TEMPERATURE PREDICTION OF SYSTEM IN PACKAGE

Hotspot thermal management of silicon-based high power hetero-integration

Extremely uneven thermal distribution due to the hotspots generating at the transistor channel regions on GaN power chip is one of the major obstacles to high power hetero-integration on silicon. In this work, a 12 mm × 18 mm × 0.7 mm embedded converging-diverging microchannel (CDMC) cooler silicon interposer (SI) is put forward to address the hotspot cooling. A 5.3 mm × 3.5 mm × 0.08 mm GaN monolithic microwave integrated circuit (MMIC) 3-stage power amplifier (PA) chip with DC heating power of ∼ 101 W was integrated on the SI to evaluate the on-chip hotspot cooling performance. The average hotspot heat flux was up to 306.8 ∼ 307.1 W/mm2, and the average chip heat flux achieved 545.4 ∼ 546.3 W/cm2. The maximum junction temperature of the GaN chip on CDMC SI was 137.2 ∼ 147.4 °C with the pressure drop of 122.8 ∼ 394.3 kPa and pumping power of 0.41 ∼ 3.29 W at 70 °C ambient temperature. The thermal and hydraulic characteristics of the CDMC SI are analyzed based on field synergy principle and thermodynamic properties using finite element method (FEM). The heat transfer coefficient (HTC) of the CDMC SI has 22.4 ∼ 35.4% increase compared with that of a typical microjet array (MJA) SI. The cooling performance and efficiency of the CDMC SI have been validated theoretically and practically to be prior to those of the MJA SI, and it is a promising solution for high power hetero-integration on silicon with brilliant hotspot thermal management capability.

Measurement method of the IGBT chip temperature fluctuation based on electrothermal model derivation

The IGBT chip temperature is an important index affecting device reliability. Due to the existence of packaging, the temperature data of the IGBT chip is difficult to obtain directly. Because the large IGBT switching frequency, the temperature changes quickly. The chip junction temperature fluctuation is too difficult to measure. Based on the Cauer electrothermal coupling model, this paper deduces the calculation formula of the IGBT chip temperature fluctuation. Through the on-stage voltage, collector current, thermal resistance, thermal capacitance, on time and off time that can be directly monitored, the chip temperature fluctuation inside the package can be calculated. Then the accuracy of the calculation formula of temperature fluctuation is verified by experimental method, and the experimental results confirm the feasibility of this method. The chip temperature fluctuation monitored by this method is the premise for the lifetime prediction and reliability research of the IGBT, which plays a great role in the engineering field.

Dynamic Modeling Framework for Evaluating Electromagnetic-Electro-Thermal Behavior of Power Conversion System During Load Operation

Abstract This study introduces a modified dynamic multiphysics modeling framework to characterize the electromagnetic-electrothermal (EET) coupled behavior of a power conversion system during a long load operation. The modeling framework extends the prior model with more comprehensive analysis and enhanced computational efficiency and modeling simplicity. This framework incorporates a fully integrated electromagnetic circuit (FIEC) model for extracting parasitics, including self and mutual inductances and also exploring their effect on the switching characteristics and power losses, and a dynamic power loss-temperature thermal (PTT) model for describing the temperature-dependent instantaneous electrical behavior and power loss. Moreover, a simple resistance-capacitance (RC) snubber circuit design is applied to prevent overvoltage and diminish voltage oscillations and spike value during the operation, and their power losses are also assessed and considered in the dynamic EET coupled modeling. Furthermore, the proposed PTT model employs an equivalent thermal RC network to calculate the chip junction temperature with a given power. Additionally, a simple power-temperature relationship derived from the FIEC cosimulation is applied for modeling simplicity and computational efficiency. This framework is tested on a three-phase inverter operating with a 180-deg conduction mode. The proposed FIEC cosimulation and computational fluid dynamics thermal models are validated by double pulse (DPT) and infrared thermography experiments, respectively. Moreover, the PTT model is validated compared with the conventional dynamic coupled electrothermal model. Finally, a design guideline for enhanced thermal performance of the tested power conversion system is sought through parametric analysis.

Effects of multi-factors on the junction temperature of LED automotive lamp chips

LED automotive lamps have become the mainstream automotive lighting equipment due to their own characteristics of energy conservation and environmental protection. However, at present, the problem of high junction temperature of LED automotive lamp chips has not been effectively solved, resulting in the decline of lighting effect and service life of LED automotive lamps, which greatly restricts the further development of LED automotive lamps. Generally, the junction temperature of LED automotive lamp chips is affected by many factors. In this paper, the effects of different factors (chip power, ambient temperature, chip distribution spacing, chip distribution shape) on the junction temperature of LED automotive lamp chip are explored by using the method of constant temperature experimental platform and ANSYS Workbench simulation; The experimental phenomena of LED junction temperature varying with different factors are analyzed in this paper. The results show that appropriately increasing the spacing of light sources in the LED automotive lamp chip can greatly reduce the chip junction temperature, and appropriately changing the distribution spacing between LED automotive lamp chips can also reduce the chip junction temperature to a certain extent. The research provides a certain basis for effectively controlling the junction temperature of LED automotive lamp chip and prolonging the life of LED automotive lamps.

Evaluation and Optimization of a Cross-Rib Micro-Channel Heat Sink.

This article presents a novel cross-rib micro-channel (MC-CR) heat sink to make fluid self-rotate. For a thermal test chip (TTC) with 100 w/cm2, the cross-ribs micro-channel were compared with the rectangular (MC-R) and horizontal rib micro-channel (MC-HR) heat sinks. The results show that, with the cross-rib micro-channel, the junction temperature of the thermal test chip was 336.49 K, and the pressure drop was 22 kPa. Compared with the rectangular and horizontal ribs heat sink, the cross-rib micro-channel had improvements of 28.6% and 14.3% in cooling capability, but the pressure drop increased by 10.7-fold and 5.5-fold, respectively. Then, the effects of the aspect ratio (λ) of micro-channel in different flow rates were studied. It was found that the aspect ratio and cooling performance were non-linear. To reduce the pressure drop, the inclination (α) and spacing (S) of the cross-ribs were optimized. When α = 30°, S = 0.1 mm, and λ = 4, the pressure drop was reduced from 22 kPa to 4.5 kPa. In addition, the heat dissipation performance of the rectangular, staggered fin (MC-SF), staggered rib (MC-SR) and cross-rib micro-channels were analyzed in the condition of the same pressure drop, MC-CR still has superior heat dissipation performance.

Numerical simulation of the single-phase immersion cooling process using a dielectric fluid in a data server

In the wake of novel technologies such as artificial intelligence (AI), machine learning (ML), internet of things (IoT) to cater to a wide spectrum of industrial applications, eventually the demand for ultra-fast processors/data centers has been on rise. In further, these novel technologies inherently result a drastic increase of power density in data centers, where air-cooling is the popularly utilized method to handle the thermal loads. The present research study involves in numerically investigating the effectiveness of single-phase immersion cooling process, an alternate solution to air-cooling method, on governing the heat load of the densely packed servers. A dielectric fluid, EC-110 is chosen for the simulation on a suitably developed CAD model of a server, of rated design power of 150 W. Four different processing unit powers of value 65 W, 90 W, 115 W and 150 W are supplied as input load to the cooling fluid in the simulation work. The condition of inlet temperature of the dielectric fluid is varied from 25℃ to 40℃ and the flow rates are varied from 0.5 lpm to 2.5 lpm. The resulting chip junction temperature in the server is estimated for different flow rates and inlet temperature conditions of the fluid, under immersion cooling technique. It proves that this cooling technique has the potential to ensure safe operation temperature of the server at low flow rates of the fluid with high inlet temperature, at high power densities.

Research on Heat Dissipation of Diode Laser Array with Sharp-angle Sink

The project is designed and analyzed for the heat sink of the semiconductor laser array, and the heat dissipation performance of the heat sink with a sharp-angled channel is simulated by the finite element method. The results show that: compared with the traditional cylindrical cavity, the sharp-angle shape cavity has a stronger heat dissipation capacity. By designing a gradual flow channel inlet and outlet size, the flow channel inlet and outlet two of the large-size and multi-bar array laser are significantly reduced. The chip junction temperature difference at the end makes the array chip wavelength difference controlled within 1.9nm, which effectively improves the absorption uniformity and efficiency of the Nd:YAG crystal in this type of pump module.

A new cooling strategy for edge computing servers using compact looped heat pipe

The rapid development of distributed edge computing system demands urgently that the thermal management solution for server CPUs in micro-data centers have the characteristics of compact structure, high performance, maintenance-free, and energy saving. This paper focuses on a new cooling concept enabled by a compact loop heat pipe. Through removing compensation chamber, selecting a spindle-shaped evaporator structure with aid of an auxiliary gradient sintered capillary wick connecting the condenser and the evaporator, this new proposed loop heat pipe module can provide high reliability operation, meanwhile maintaining high thermal performance. Under forced air cooling, it is demonstrated that the 4 mm thick loop heat pipe module with finned tube condenser could dissipate a heat load of 150 W under a wide fan voltage range from 12 V to 24 V at tested directions when the chip junction temperature was below 85 °C, and could manage a heat load up to 275 W without dry-out. The proposed new loop heat pipe module with finned tube condenser is a potential solution to cool edge-computing server CPUs.