Junctionless Field Effect Transistor Research Articles

A computational study of a carbon nanotube junctionless tunneling field-effect transistor (CNT-JLTFET) based on the charge plasma concept

In this work, a carbon nanotube junctionless tunnel field-effect transistor has been proposed and investigated. The presented structure uses two isolated gates with the same work function (main gate (MG) and P-gate (PG)) which are separated by a 3 nm SiO2 spacer. PG has a constant voltage and a constant length of 0.4 V and 12 nm, respectively which has been used for electrically activation of the source region to behave like a tunnel FET. Simulations show that in comparison with the conventional carbon nanotube tunnel field-effect transistor (CNT-TFET) and carbon nanotube tunnel field-effect transistor with hetero-gate dielectric (HGD-CNT-TFET) suggested structure has significant higher ON current and improvement in ambipolar behavior. Furthermore, analog characteristics like unity gain frequency (ft) and transconductance (gm) have been improved considerably.

Hybrid P-Channel/N-Substrate Poly-Si Nanosheet Junctionless Field-Effect Transistors With Trench and Gate-All-Around Structure

This paper demonstrates the gate-all-around P/N hybrid nanosheet p-channel junctionless field-effect transistors (GAA NS-JLFET) with trench and raised source and drain structure. The GAA NS-JLFET exhibits the superior electrical properties, including high field-effect mobility (18.9 cm2/Vs), high on/off current ratio (>5 × 106), steep subthreshold slope (136 mV/dec.), and low DILB (60 mV/V). The high mobility and steep subthreshold slope of this GAA NS-JLFET indicates that the conducting hole filled the whole thin nanosheet channel. This GAA NS-JLFET is simple to fabricate and highly favorable for use in advanced system-on-panel and three-dimensional stacked ICs applications.

Performance evaluation of normally ON/OFF junctionless vertical channel GaN FET

GaN vertical channel junction field-effect transistor (VC-JFET) is a relatively new technology, which is particularly suitable for high-power applications. In these devices, the channel is formed between two p-GaN current blocking layers which is a complex and costly process. In addition, various traps and defects get introduced during the fabrication of p-GaN layers. The traps and defects near the interface of the p-GaN layer and n-GaN channel can deteriorate the device performance. Therefore, for reducing the fabrication complexity with enhanced device performance, a normally ON/OFF GaN vertical channel junctionless field-effect transistor (VC-JLFET) is proposed in this paper. The results are compared against conventional GaN VC-junction field-effect transistor (VC-JFET) of the equal dimensions and doping concentrations. The absence of p–n junction at source and drain in the proposed device offers less fabrication complexity, cost, and thermal budget as compared to the referenced device. The proposed device provides more than four times drain current ( $$8.37\times 10^{-6}$$ A/μm) as compared to the referenced device ( $$1.9 \times 10^{-6}$$ A/μm) at similar physical and bias conditions. The obtained values of ON resistance, trans-conductance, unity gain bandwidth frequency, and breakdown voltage for the proposed normally ON device (at Lap = 0.9 μm, Vth = −3.5 V, VG = −1V, VD = 1 V) are 5.63 × 103 Ω/μm, 6.99 × 10−7 S/μm, 1.56 × 108 Hz and 700 V, respectively. While in normally OFF mode, the obtained values of parameters such as threshold voltage, ON resistance, breakdown voltage, and drain current are 2 V, $$1.56 \times 10^{6}$$ Ω/μm, greater than 1000 V and $$1.54 \times 10^{-6}$$ A/μm, respectively. The normally OFF VC-JLFET is achieved by gate work-function engineering in conjunction with doping optimization.

A novel low leakage saddle junctionless FET with assistant gate

AbstractIn this paper, a novel low leakage saddle junctionless field effect transistor with assistant gate is proposed. Its electrical properties have been extensively investigated by studying the influence resulting from variation of design parameters, such as the thickness of assistant gate, oxide layer thickness between the main and assistant gate, extension height of S/D contact, and the voltage of assistant gate. Compared with conventional structure, the proposed saddle junctionless field effect transistor with assistant gate shows much better performance at off state. The leakage current is effectively restrained, and the Ion‐Ioff ratio is largely improved. Design parameter optimization has also been performed.

Microscopic simulation of RF noise in junctionless nanowire transistors

A deterministic solver for the analysis of microscopic noise and small-signal fluctuations in junctionless nanowire field-effect transistors is presented, which is based on a self-consistent and simultaneous solution of the Poisson/Schrodinger/Boltzmann equations. It is verified that the numerical framework fulfills the vital properties of reciprocity and passivity in the small-signal sense, and yields Johnson–Nyquist noise under equilibrium conditions. Key figures such as the cutoff frequency, drain excess noise factor, the Fano factor, and gate/drain correlation coefficient are presented at various bias conditions. In this work we show that similar to the inversion-mode MOSFETs, the gate and drain current noises mainly stem from the warm electrons at the source side, whereas the hot electrons do not have a significant contribution. Also, our results show that the device behaves similar to long-channel FETs in terms of its excess noise even for a channel length of 10 nm, due to the strong control of its electrostatics by the all-around gate.

Enhancement of off-state characteristics in junctionless field effect transistor using a field plate**Project supported by the National Natural Science Foundation of China (Grant No. 61704130), the Fundamental Research Funds for the Central Universities, China (Grant No. 20101166085) and the Opening Project of Key Laboratory of Microelectronic Devices & Integrated Technology from Institute of Microelectronics, Chinese Academy of Sciences (Grant No.

In this paper, a novel junctionless field effect transistor (JLFET) is proposed. In the presence of a field plate between gate and drain, the gate-induced drain leakage (GIDL) effect is suppressed due to the decrease of lateral band-to-band tunneling probability. Thus, the off-state current Ioff, which is mainly provided by the GIDL current, is reduced. Sentaurus simulation shows that the Ioff of the new optimized JLFET is reduced by ∼ 2 orders and its sub-threshold swing can reach 76.8 mV/decade with little influence on its on-state current Ion, so its Ion/Ioff ratio is improved by 2 orders of magnitude compared with that of the normal JLFET. Optimization of device parameters such as Φfps (the work difference between field plate and substrate) and LFP (the length of field plate), is also discussed in detail.

Subthreshold Modeling of Tri-Gate Junctionless Transistors With Variable Channel Edges and Substrate Bias Effects

In this paper, subthreshold channel potential, current, swing, threshold voltage, and drain-induced barrier lowering models of short-channel tri-gate junctionless field-effect transistors are presented. The models incorporate the effects of both substrate-induced surface potential and variable edges of channel. The quasi-3-D approach is used for the modeling of minimum of channel potential that is subsequently used in the drift–diffusion equation to obtain the current expression in subthreshold regime. Threshold voltage and subthreshold swing models are also based on the minimum of channel potential. The analytical results are compared with the simulation data obtained using 3-D visual TCAD device simulator from Cogenda Pvt., Ltd.

Two-Dimensional MX2 Semiconductors for Sub-5 nm Junctionless Field Effect Transistors.

Two-dimensional transitional metal dichalcogenide (TMDC) field-effect transistors (FETs) are proposed to be promising for devices scaling beyond silicon-based devices. We explore the different effective mass and bandgap of the channel materials and figure out the possible candidates for high-performance devices with the gate length at 5 nm and below by solving the quantum transport equation self-constantly with the Poisson equation. We find that out of the 14 compounds, MoS2, MoSe2, and MoTe2 may be used in the devices to achieve a good subthreshold swing and a reasonable current ON-OFF ratio and delay. Our work points out the direction of further device optimization for experiments.

Erratum to: Designing a Hetrostructure Junctionless-Field Effect Transistor (HJL-FET) for High-speed Applications

Erratum to: Designing a Hetrostructure Junctionless-Field Effect Transistor (HJL-FET) for High-speed Applications

Fabrication and characterization of novel gate-all-around polycrystalline silicon junctionless field-effect transistors with ultrathin horizontal tube-shape channel

In this paper, we report on a novel fabrication process for the production of junctionless field-effect transistors with an ultrathin polycrystalline silicon (poly-Si) tube channel in a gate-all-around (GAA) configuration. The core of the poly-Si tube channel is filled with either a silicon nitride or a silicon oxide layer, and the effects of the core layers on the device characteristics are evaluated. The devices show excellent switching performance, thanks to the combination of the ultrathin tube channel and the GAA structure. Hysteresis loops in the transfer characteristics of the nitride-core devices are observed, owing to the dynamic trapping of electrons in the nitride core.

Hybrid N-Type Poly-Si Ultra-Thin Nanowire Shell Channel with P-Substrate Structure by Electron Beam Lithography Adjustment for Junctionless Field-Effect Transistors

This study proposes a new hybrid N channel/P substrate for junctionless field-effect transistors (JL-FET) by using electron beam lithography adjustment for the shell structure. The nanowire (NW) shell JL-FET exhibits the superior electrical properties, including high ON/OFF current ratio of 6 × 106, low subthreshold swing (SS) of 95 mV/decade and drain-induced barrier lowering value (DIBL) of 50 mV/V. This NW shell structure JL-FET is simple to fabricate, and highly favorable for use in advanced System-on-panel (SoP) and three-dimensional (3-D) stacked IC applications.

Design of GaAs Based Junctionless Field Effect Transistor and Its Performance Evaluation

Design of GaAs Based Junctionless Field Effect Transistor and Its Performance Evaluation

Design Optimization and Analysis of InGaAs-Based Gate-All-Around (GAA) Junctionless Field-Effect Transistor (JLFET)

Design Optimization and Analysis of InGaAs-Based Gate-All-Around (GAA) Junctionless Field-Effect Transistor (JLFET)

GaN-Based Junctionless Field-Effect Transistor with Hetero-Gate Dielectric for Enhancement of Direct Current and Radio Frequency Performance

GaN-Based Junctionless Field-Effect Transistor with Hetero-Gate Dielectric for Enhancement of Direct Current and Radio Frequency Performance

A Surface Potential and Threshold Voltage Model Including Quantum Mechanical Effects for a Dual Material Double Gate Junctionless Field Effect Transistor (DMDG-JLFET)

A Surface Potential and Threshold Voltage Model Including Quantum Mechanical Effects for a Dual Material Double Gate Junctionless Field Effect Transistor (DMDG-JLFET)

Designing a hetrostructure junctionless-field effect transistor (HJL-FET) for high-speed applications

This paper explores the impacts of both the strained silicon layer thickness, D, and germanium mole fraction, X, on the electrical characteristics of a heterostructure junctionless (HJL)-FET by a numerical simulator. The gate controllability on the Si1−X Ge X layer has been increased by reducing D for a given X, hence, OFF-state current decreases. The permittivity factor increasing prevails to the band gap reducing in the Si0.3Ge0.7 layer, for D = 0.5 nm. As a result, in a 15 nm channel length, the OFF-state current of HJL-FET with D = 0.5 nm and X = 0.7 is improved by 95%, as compared to that of the regular JL-FET. Therefore, D and X parameters can be considered to reduce the OFF-state current of HJL-FET, even without pushing the gate to a large negative voltage. We propose a novel “Modified HJL-FET (MHJL-FET)” structure which improves the subthreshold slope (SS) in comparison with HJL-FET, by employing the doping engineering. The Si1−X Ge X layer of MHJL-FET has a lower doping density in comparison with the strained silicon layer. The doping engineering not only reduces SS by 10%, but also increases the ION/IOFF ratio two orders of magnitude, for 10 nm channel length. The benchmarking results indicate that the MHJL-FET device is promising for future logic transistor applications.

A Threshold Voltage Model of Tri-Gate Junctionless Field-Effect Transistors Including Substrate Bias Effects

In this paper, the influence of substrate bias voltage and substrate-induced surface potential (SISP) on threshold voltage of tri-gate junctionless field-effect transistors (TG-JLFETs) has been investigated. For this purpose, a quasi-3-D threshold voltage model of TG-JLFETs is presented considering the effects of both back-bias voltage and a lightly doped substrate. To incorporate the effect of SISP on the threshold voltage, the boundary conditions at the silicon–buried oxide interface have been modified accounting for the potential difference between substrate surface and substrate bulk. Model results are compared with the simulation results obtained using 3-D visual TCAD device simulator from Cogenda.

Experimental and Simulation Study of Silicon Nanowire Transistors Using Heavily Doped Channels

The experimental results from 8 nm diameter silicon nanowire junctionless field-effect transistors with gate lengths of 150 nm are presented that demonstrate on-currents up to 1.15 mA/μm for 1.0 V and 2.52 mA/μm for 1.8 V gate overdrive with an off-current set at 100 nA/μm. On- to off-current ratios above 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> with a subthreshold slope of 66 mV/dec are demonstrated at 25 °C. Simulations using drift-diffusion which include density-gradient quantum corrections provide excellent agreement with the experimental results. The simulations demonstrate that the present silicon-dioxide gate dielectric only allows the gate to be scaled to 25 nm length before short-channel effects significantly reduce the performance. If high-K dielectrics replace some parts of the silicon dioxide then the technology can be scaled to at least 10 nm gatelength.

Performance improvement of junctionless field effect transistors using p-GaAs/AlGaAs heterostructure

The performance analysis of junctionless (JL) gate-all-around (GAA) metal oxide semiconductor field effect transistors (MOSFETs) is investigated using the Non-Equilibrium Green's Function (NEGF) formalism. The main problem of JL transistors is found to be the OFF-state current. In the present work, the OFF-state current of such devices is decreased by choosing channel materials with a large band gap and heavy effective mass. Our simulation results show that the OFF-state current of JL transistors with p-type GaAs is less than that of n-type GaAs. Plus, the heterostructure (HES) channel is proposed in this study for improving the device characteristics of JL-FETs as compared to homostructure (HOS). Therefore, p-type GaAs and GaAs/AlGaAs are used as the channel material for HOS and HES devices, respectively. The simulation is performed for different thicknesses of GaAs and AlGaAs with a fixed diameter of 5 nm for the nanowire. It is shown that the optimum electronic characteristics of HES devices is achieved when the thicknesses of GaAs and AlGaAs layers are chosen to be 0.5 nm and 4 nm, respectively. OFF-state current (IOFF) of 5.32 × 10−16 A, ON-state current (ION) of 6.44 × 10−6 A, ON/OFF current ratio (ION/IOFF) of 1.21 × 1010, subthreshold slope (SS) of 60.8 mV/dec, drain induced barrier lowering (DIBL) of 4.6 mV/V, and threshold voltage (VTH) of 330 mV are obtained for the proposed HES JL-GAA-FET.

Introduction of a metal strip in oxide region of junctionless tunnel field-effect transistor to improve DC and RF performance

Achieving steeper subthreshold slope and high ON–OFF current ratio (\(I_{\mathrm{ON}}/I_{\mathrm{OFF}}\)) is essential for use of semiconductor devices in switching applications. It is well known that tunnel field-effect transistors face serious issues related to low ON-state current and poor radio frequency (RF) response. We report herein a unique method for realizing a sharp tunneling junction in a charge plasma-based junctionless tunnel field-effect transistor by embedding a metal strip in the oxide region near to the source–channel connection. This modulates the carrier concentration profile at the source–channel interface, making it abrupt. This steeper source–channel tunneling junction results in a reduced tunneling barrier and increased flow of charge carriers at the junction. Furthermore, electron transfer along the channel is accounted for using postprocessing based on the drift–diffusion equations as well as the band-to-band tunneling current. This phenomenon contributes to the improved direct-current (DC) characteristics of the device. Selection of a metal with an appropriate work function for the strip can improve the subthreshold swing and threshold voltage (\(V_{\mathrm{th}}\)) of the device. The increased charge carrier tunneling rate at the junction also results in a huge improvement in RF parameters of the device, including cutoff frequency (\(f_{T}\)), gain–bandwidth product, and transit time (\(\tau \)).