Abstract
AbstractIn this paper, a novel low leakage saddle junctionless field effect transistor with assistant gate is proposed. Its electrical properties have been extensively investigated by studying the influence resulting from variation of design parameters, such as the thickness of assistant gate, oxide layer thickness between the main and assistant gate, extension height of S/D contact, and the voltage of assistant gate. Compared with conventional structure, the proposed saddle junctionless field effect transistor with assistant gate shows much better performance at off state. The leakage current is effectively restrained, and the Ion‐Ioff ratio is largely improved. Design parameter optimization has also been performed.
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