Junction Field Effect Transistor Research Articles

An Analytical Subthreshold I–V Model of SiC Double Gate JFETs

ABSTRACTSiC double gate (DG) junction field effect transistor (JFET) is promising for low‐noise and high‐temperature electronics. Existing studies indicate that JFETs can be considered a special case of MOSFETs when the oxide layer thickness approaches zero. In this article, we exploited the structural similarity between the DG JFETs and the DG MOSFETs. By obtaining the 2D Poisson's equation for the DG MOSFETs and deriving the limits, we developed a model for calculating the channel current of SiC DG JFETs in the subthreshold region. The model is derived from device physics, requiring no fitting parameters and offering relatively low computational complexity. The results indicate that, whether for enhancement mode or depletion mode JFETs, the calculated values of this model are in good agreement with the 2D numerical analysis results obtained from Silvaco Atlas. Moreover, for enhancement mode JFETs, even when significant short‐channel effects occur, the subthreshold current can still be well predicted. In addition, the model displays predictive capability for the depletion‐mode JFETs.

Reconfigurable van der Waals Junction Field Effect Transistor with Anchored Threshold and Enhanced Subthreshold Swing for Complementary Logic.

The emergence of reconfigurable field effect transistors has introduced a more efficient method for realizing reconfigurable circuits, significantly lowering hardware overhead and enhancing versatility. However, these devices often suffer from asymmetric transfer curves, impacting logic gate performance and reliability. This work investigates the use of the van der Waals junction field effect transistor (JFET) for reconfigurable circuit applications. We present a reconfigurable JFET realized through WSe2/MoS2 van der Waals integrated heterojunctions with an optimized polarity gate design that effectively addresses the issues of unmatched threshold voltages between n- and p- FETs while also anchoring threshold voltages and reducing subthreshold swing. A complementary reconfigurable JFET inverter with the proposed gate design was demonstrated, showcasing excellent switching characteristics, symmetric transfer characteristics, and reduced power consumption, achieving a noise margin of 96.3% and a high gain of 153.82. The study further demonstrates the construction of reconfigurable NOR/NAND and XOR/XNOR logic gates with symmetric profiles and sharp switching, underscoring the versatility and effectiveness of the proposed approach. These findings highlight the potential of WSe2/MoS2 JFETs in advancing low-power, high-performance, reconfigurable electronic circuits within the CMOS framework.

Enhancing Normally-Off P-GaN Gate HEMTs Performance with Composite GaN/AlN/AlGaN Blocking Layers

Purpose of Work Due to the excellent figure of merit and reliable normally-off functionality, p-GaN gate HEMTs have been superior to traditional silicon-based components, especially with higher breakdown voltage and lower RON [1]. Despite the excellent performance of p-GaN gate HEMTs, there are still some significant challenges that require improvement. Firstly, reducing gate leakage current via the incorporation of an additional dielectric layer beneath the gate provides an effective method for reducing leakage current and enhancing gate drive voltage [2]. Secondly, during the epitaxial growth of the p-GaN capping layer, an undoped GaN (u-GaN) blocking layer needs to be considered in the p-GaN structure to achieve optimal Mg activation by MOCVD. This layer acts as a blocking function to mitigate Mg out-diffusion into the AlGaN barrier and/or GaN channel, thus preventing 2DEG degradation [3]. In this work, we demonstrated a novel composite blocking layer comprising u-GaN/AlN/AlGaN for normally-off p-GaN gate HEMTs. Compared with traditional p-GaN gate HEMT without a composite blocking layer, the IDMAX current is significantly increased by 37% and RON is reduced by 23%. This reason can be attributed to the introduction of the u-GaN as a blocking layer under p-GaN which effectively mitigates Mg diffusion in the capping layer, thus solving its deleterious effects. Approach The fabrication of p-GaN gate HEMTs followed a standardized base structure which included an identical AlN seed layer, an AlGaN buffer layer, and an Al0.18Ga0.82N barrier/GaN channel layer. To study the effects of the AlN spacer and u-GaN blocking layer on device characteristics, the epitaxial structure of the active layer was designed for comparative analysis. These designed structures were denoted to "Device A" without an AlN spacer and u-GaN layer, "Device B" with an AlN spacer but without a u-GaN layer, and "Device C" with including an AlN spacer and a u-GaN layer in Fig. 1 (a). For normally-off p-GaN HEMTs, mesa isolation was fabricated by ICP-RIE. Next, a Schottky contact was formed using a Ti/Al/Ni layer by an E-Gun. A 15 nm Al2O3 layer was deposited as dielectric by ALD, followed by 50 nm Si3N4 passivation by PECVD. Ohmic contact was fabricated through Ti/Al/Ti metal stack and RTA in the N2 atmosphere at 825°C for the 30s. The final steps include a gate field plate, a 150 nm Si3N4 passivation layer, and contact hole openings for the Ti/Al metal stack as electrode pads in Fig. 1 (b). Results and Significance In Fig 2 (a), the VTH for devices A, B, and C were determined to be 1.5 V, 1.4 V, and 1.0 V, respectively. IDMAX current at the VG of 6 V was observed to be 198 mA/mm for Device A, 241 mA/mm for Device B, and 272 mA/mm for Device C, and maximum transconductance (Gm,MAX)values of 51.2 mS/mm, 72.7 mS/mm, and 77.3 mS/mm, respectively. Device A exhibited the subthreshold slope (SS) value of 121 mV/dec, while Device B had 117 mV/dec, and Device C demonstrated the lowest SS value of 102 mV/dec. Notably, Device C exhibits excellent gate control efficiency which is attributed to the introduction of the u-GaN barrier layer that effectively mitigates Mg diffusion into the AlGaN barrier and/or GaN channel, thereby reducing band-to-band leakage. Fig. 2 (b) shows the RON of the devices, with values of 14.5 Ω-mm, 12.1 Ω-mm, and 11.1 Ω-mm for devices A, B, and C. Devices B and C contain AlN spacer layers and exhibit lower RON compared to device A. It is worth noting that device C has the u-GaN barrier layer and effective AlN spacer, which not only mitigates Mg diffusion into the AlGaN/GaN channel but also enhances the interface polarization field, thereby injecting more electrons into the 2DEG channel and improving turn-on resistance.[1] A. C. Liu, Y. Y. Lai, H. C. Chen, and H. C. Kuo," A Brief Overview of the Rapid Progress and Proposed Improvements in Gallium Nitride Epitaxy and Process for Third-Generation Semiconductors with Wide Bandgap," micromachines., vol. 14, pp. 764, 2023.[2] M. Jia, B. Hou, L. Yang, F. Jia, X. Niu, J. Du, Q. Chang, M. Zhang, M. Wu, and X. Zhang,"High VTH and Improved Gate Reliability in P-GaN Gate HEMTs with Oxidation Interlayer," IEEE Electron Device Lett., vol. 44, pp. 1404-1407, 2023.[3] T. Pu, Q. Huang, T. Zhang, J. Huang, X. Li, L. Li, X. Li, L. Wang, and J. P. Ao,"Normally-off AlGaN/GaN heterostructure junction field-effect transistors with blocking layers," Superlattices Microstruct., vol. 120, pp. 448-453, 2018. Figure 1

Infrared photoinduced force near-field spectroscopy of silicon carbide

Silicon carbide (SiC) is a promising microelectronic semiconductor with an infrared response that depends on factors such as polytype, growth conditions, and structuring. Recent advances in infrared nano-imaging techniques provide new opportunities to characterize thin films at the nanoscale. We performed tip-enhanced near-field spectral characterization on various 4H-SiC sample surfaces using photoinduced force microscopy (PiFM). The near-field spectra feature a peak associated with a surface phonon polariton (SPhP) resonance, which proves to be highly sensitive to the material’s surface quality. Interestingly, we found that the power absorption at the tip-sample junction, enhanced by the effective tip polarizability, can account for these PiFM spectra, resulting in a blend of both dispersive and dissipative spectral line shapes. As a potential application, a junction-field effect transistor was imaged to evaluate the technique’s ability to map the surface of different p- and n-doped areas, demonstrating high sensitivity and spatial resolution compared to Raman analysis.

DNA adsorption monitoring with interdigital open-gate junction field effect transistor for DNA storage applications: MD modeling, design, and experimental results

This paper introduces a novel portable sensing platform designed to explore the intricate interaction between DNA molecules and silicon dioxide (SiO2) coated on a field effect transistor (FET), bearing profound implications for a spectrum of life science applications, particularly DNA storage. In-silico molecular dynamic (MD) simulations are employed to gain insights into the effects of DNA on the FET surface's potential under extreme conditions of dehydration of double-stranded DNA (dsDNA), verifying its capacity to generate surface charge when dehydrated due to the evaporation of droplets. The platform is comprised of a backgated interdigital open gate junction FET (ID-OGJFET) fabricated through an innovative electronic sensing platform foundry and accompanied by an electronic interface system incorporated with a fluidic sample holder that reads the surface charge on the sensor induced by negatively charged nucleotides in dsDNA and single-stranded DNA (ssDNA). This novel ID-OGJFET sensor coated with native SiO2 enables a direct-on-channel sensing area of >16 mm2 without top gate extension for the target application, working at low back gate voltage (<0.4 V) for adsorption analysis in the dry mode. Our study involves designing, synthesizing, and introducing DNA sequences onto the chip surface at various concentrations. This paper presents and discusses experimental results that align with MD simulations, elucidating the impact of DNA's intrinsic charge on the chip's surface under extreme dehydration conditions. These findings pave the way for developing a portable charge-sensitive DNA monitoring system, particularly in the emerging physical storage of DNA.

Quantum enhanced Josephson junction field-effect transistors for logic applications

Josephson junction field-effect transistors (JJFETs) have recently re-emerged as promising candidates for superconducting computing. For JJFETs to perform Boolean logic operations, the so-called gain factor αR must be larger than 1. In a conventional JJFET made with a classical channel material, due to a gradual dependence of superconducting critical current on the gate bias, αR is much smaller than 1. In this Letter, we propose a new device structure of quantum enhanced JJFETs in a zero-energy-gap InAs/GaSb heterostructure. We demonstrate that, due to an excitonic insulator quantum phase transition in this zero-gap heterostructure, the superconducting critical current displays a sharp transition as a function of gate bias, and the deduced gain factor αR ∼ 0.06 is more than 50 times that (∼0.001) reported in a classical JJFET. Further optimization may allow achieving a gain factor larger than 1 for logic applications.

MoS2/GaN Junction Field‐Effect Transistors with Ultralow Subthreshold Swing and High On/Off Ratio via Thickness Engineering for Logic Inverters

AbstractIn recent years, 2D/3D heterojunction electronic devices have attracted considerable attention. As the size decreases, enhancing the speed of MOSFETs, reducing the subthreshold swing (SS), and lowering the power consumption (P) have become challenging. Therefore, in the post‐Moore era, in response to the continuation of Moore's law, junction field‐effect transistors (JFETs) based on mixed‐dimensional MoS2/GaN heterojunctions are proposed via thickness engineering. Accordingly, flat hetero interface and large potential barrier height of 5 eV across the heterojunction, an ultra‐low SS of 60.9 mV dec−1 (The Boltzmann limit is 60 mV dec−1) is achieved at Vds = 0.1 V when the MoS2 thickness is 10 nm. Additionally, a high Ion/Ioff ratio of 107 and a saturation current density (Jds) of 0.16 µA µm−1 is achieved. As the thickness of MoS2 increased from 6 to 16 nm, the working mode transitioned from enhancement mode to depletion mode. The depletion region across the channel is verified using computer‐aided design technology. Finally, an N‐type load inverter with a maximum voltage gain of 4 and a minimum static P of 25 nW is applied. Overall, the work provides a universal strategy for constructing a series of high‐performance transition metal dichalcogenide/GaN JFETs.

Research on anti-single event ability and reinforcement method of SiC MOSFET

Abstract High-voltage silicon carbide (SiC) metal-oxide field-effect transistor (MOSFET) is limited by its ability to resist single event effect (SEE), so it is necessary to study its ability to resist SEE and form an effective reinforcement method. In this paper, it will be studied that how the influence of device structure on the anti-single event ability of SiC MOSFET from the irradiation experiment, and the safe working area of single event leakage degradation of the device is examined. It is found that the width of junction field effect transistor (JFET) and P- type ohmic contact interval both affect the SEE of the device. The SEE mechanism of the device is analyzed based on the experimental results. And the failure caused by local electrothermal stress concentration is confirmed. In view of this mechanism, the reinforced structure is designed with SiO2 barrier layer added in the single event sensitive area, the electrical stress is effectively alleviated, and the peak drain current is reduced by about 18%.

Characteristics of 2N4416 Si JFETs for radiation spectrometer charge sensitive preamplifiers

The input transistors (JFETs) of feedback resistor-less charge sensitive preamplifiers (CSPs), for photon and charged particle counting radiation spectrometers, that use semiconductors as their detectors, are operated in an unusual forward biased mode; consequently, manufacturer datasheets cannot necessarily be relied upon, as they do not specify the characteristics of the JFETs when they are operated with the gate-to-source junction forward biased. This experimental study, in which 165 2N4416 and 2N4416A NJ26 silicon junction field effect transistors (JFETs) were electrically characterised at ambient laboratory temperature, focused on the JFETs’ performances in the context of their use as input transistors of feedback resistor-less charge sensitive preamplifiers (CSPs). The experimental study found evidence which supports much of the common practice of the skilled CSP designer but which had not been documented with results in the open literature until now. This includes, inter alia, that: the 2N4416 performs better than the 2N4416A; not all transistors even of the same type have comparable performance when operated in forward bias mode; only a small proportion of 2N4416 and 2N4416A transistors are of desirable performance characteristics for CSPs; and, individual screening of each candidate JFET is required if an optimally performing CSP is to be produced – even when using JFETs of the same type from the same batch. The methodology and analysis documented here will also be useful to researchers developing new wide bandgap semiconductor JFETs for high temperature tolerant and radiation-hard CSPs.

Quantum Enhanced Josephson Junction Field-Effect Transistors for Logic Applications

The need of data centers for cloud and network computing has dramatically increased power consumption. In 2014, data centers in the U.S. consumed an estimated 70 billion kWh, representing about 1.8% of total U.S. electricity consumption [“United States Data Center Energy Usage Report," published in June 2016 and supported by the Federal Energy Management Program of the U.S. Department of Energy]. Worldwide, the International Energy Agency estimates that currently about 1% of all global electricity is used by data centers. It is expected that by 2030 the electricity use of information and communications technology may exceed 20% of all global electricity. The microelectronics industry has been focusing on aggressively shrinking the size of logic and memory devices to reduce power consumption. However, this scaling is going to eventually stop as we approach the fundamental materials limit. Moreover, the power dissipation due to the increased number of transistors is also expected to be a limiting factor for processor performance.Superconducting computing has been suggested as a promising approach for low-energy, power-efficient circuit applications. Moreover, using superconducting interconnects can further reduce power consumption. Josephson junction field-effect transistors (JJFET, Fig. a) have recently emerged as a promising candidate for superconducting computing. JJFETs are particularly useful for low power consumption applications as they are operated with, in the superconducting regime, zero voltage drop across its source and drain. Feasibility of using JJFETs for logic operations has been explored [1]. Moreover, high noise margin has been demonstrated for the logic inputs [2]. Compared to single flux quantum approach, JJFET circuits can use designs similar to conventional silicon MOSFETs [1].For JJFETs to perform logic operations, the gain-factor (αR) value must be larger than 1. Here αR = dIc/d(Vg–Vt) x πΔ/Ic, Δ is the superconducting gap, Vg the gate bias voltage, Vt the threshold voltage. Ic ∝ exp(-L/ξc) is the critical supercurrent, where L is the channel length and ξc the carrier coherence length [3]. In a conventional JJFET, ξc ∝ (Vg–Vt)0.5 (Fig. b), and thus dIc/d(Vg–Vt) is small (Fig. c). This translates to a requirement of superconducting transition temperature of ~ 400K for αR larger than 1, far exceeding any recorded critical temperatures. As such, it is impossible to use conventional JJFETs for logic operations.Here, we propose a novel type of JJFET based on quantum phase transition, such as the excitonic insulator (EI) transition in a type-II InAs/GaSb heterostructure [4,5], for low-energy, power-efficient logic applications. The nature of the collective phenomenon in the EI quantum phase transition can provide a sharp transition of the supercurrent states (e.g., ξc ∝ (Vg–Vt)5 and dIc/d(Vg–Vt) very large, as shown in Figs. b and c, respectively) which will enable αR larger than 1 with an easy-to-achieve superconducting transition temperature of ~ 40K. In this talk, we will present some preliminary results demonstrating that indeed the gain factor in these quantum enhanced JJFETs can be greatly improved, thus making them a promising candidate for logic applications.Sandia National Laboratories is a multimission laboratory managed and operated by NTESS LLC, a wholly owned subsidiary of Honeywell International Inc. for the U.S. DOE’s NNSA under contract DE-NA0003525. This paper describes objective technical results and analysis. Any subjective views or opinions that might be expressed in the paper do not necessarily represent the views of the U.S. DOE or the United States Government.

Demonstration of a lateral p-NiO/n-GaN JFET fabricated by selective-area regrowth

In this paper, we demonstrated experimentally a lateral GaN-based junction field effect transistor (JFET). A selective area regrowth of p-NiO on the as-grown n-GaN channel layer was developed by magnetron sputtering at room temperature to form the p–n junction. A self-aligned gate process and a post metal annealing process were employed to improve the device performances. The measured results show that the annealed JFET exhibits an ON/OFF ratio exceeding 106 and a higher breakdown voltage up to 814 V without any terminal structure. The breakdown voltage is determined by the reverse breakdown of parasitic PN junction between gate and drain. Further, the threshold voltage of the p-NiO/n-GaN JFET exhibits excellent temperature stability in the range of 300–500 K.

Defect Engineering of MoTe2 via Thiol Treatment for Type III van der Waals Heterojunction Phototransistor.

Molybdenum ditelluride (MoTe2) nanosheets have displayed intriguing physicochemical properties and opto-electric characteristics as a result of their tunable and small band gap (Eg ∼ 1 eV), facilitating concurrent electron and hole transport. Despite the numerous efforts devoted to the development of p-type MoTe2 field-effect transistors (FETs), the presence of tellurium (Te) point vacancies has caused serious reliability issues. Here, we overcome this major limitation by treating the MoTe2 surface with thiolated molecules to heal Te vacancies. Comprehensive materials and electrical characterizations provided unambiguous evidence for the efficient chemisorption of butanethiol. Our thiol-treated MoTe2 FET exhibited a 10-fold increase in hole current and a positive threshold voltage shift of 25 V, indicative of efficient hole carrier doping. We demonstrated that our powerful molecular engineering strategy can be extended to the controlled formation of van der Waals heterostructures by developing an n-SnS2/thiol-MoTe2 junction FET (thiol-JFET). Notably, the thiol-JFET exhibited a significant negative photoresponse with a responsivity of 50 A W-1 and a fast response time of 80 ms based on band-to-band tunneling. More interestingly, the thiol-JFET displayed a gate tunable trimodal photodetection comprising two photoactive modes (positive and negative photoresponse) and one photoinactive mode. These findings underscore the potential of molecular engineering approaches in enhancing the performance and functionality of MoTe2-based nanodevices as key components in advanced 2D-based optoelectronics.

Switching and Frequency Response Assessment of Photovoltaic Drivers and Their Potential for Different Applications.

Newly introduced Photovoltaic (PV) devices, featuring a built-in chip with an illuminating Light Emitting Diode (LED), have emerged in the commercial market. These devices are touted for their utility as both low- and high-side power switch drivers and for data acquisition coupling. However, comprehensive knowledge and experimentation regarding the limitations of these Photovoltaic Drivers in both switching and signal processing applications remain underexplored. This paper presents a detailed characterization of a Photovoltaic Driver, focusing on its performance under resistive and capacitive loads. Additionally, it delineates the device's constraints when employed in signal processing. Through the analysis of switching losses across various power switches (Silicon and Silicon Carbide) in both series and parallel driver configurations, this study assesses the driver's efficacy in operating Junction Field-Effect Transistors (JFETs). Findings suggest that Photovoltaic Drivers offer a low-cost, compact solution for specific applications, such as high-voltage, low-bandwidth measurements, and low-speed turn-on with fast turn-off power switching scenarios, including solid-state switches and hot-swap circuits. Moreover, they present a straightforward, cost-effective method for driving JFETs, simplifying the circuit design and eliminating the need for an additional negative power source.

A Reconfigurable All-Optical-Controlled Synaptic Device for Neuromorphic Computing Applications.

Retina-inspired visual sensors play a crucial role in the realization of neuromorphic visual systems. Nevertheless, significant obstacles persist in the pursuit of achieving bidirectional synaptic behavior and attaining high performance in the context of photostimulation. In this study, we propose a reconfigurable all-optical controlled synaptic device based on the IGZO/SnO/SnS heterostructure, which integrates sensing, storage and processing functions. Relying on the simple heterojunction stack structure and the role of energy band engineering, synaptic excitatory and inhibitory behaviors can be observed under the light stimulation of ultraviolet (266 nm) and visible light (405, 520 and 658 nm) without additional voltage modulation. In particular, junction field-effect transistors based on the IGZO/SnO/SnS heterostructure were fabricated to elucidate the underlying bidirectional photoresponse mechanism. In addition to optical signal processing, an artificial neural network simulator based on the optoelectrical synapse was trained and recognized handwritten numerals with a recognition rate of 91%. Furthermore, we prepared an 8 × 8 optoelectrical synaptic array and successfully demonstrated the process of perception and memory for image recognition in the human brain, as well as simulated the situation of damage to the retina by ultraviolet light. This work provides an effective strategy for the development of high-performance all-optical controlled optoelectronic synapses and a practical approach to the design of multifunctional artificial neural vision systems.

Study of drain-induced channel effects in vertical GaN junction field-effect transistors

A normally-off vertical gallium nitride (GaN) junction field-effect transistor (JFET) is demonstrated in this work. The device shows an on/off current ratio of 3.6 × 1010, a threshold voltage (V TH) of 1.64 V, and a specific on-resistance (R ON,SP) of 1.87 mΩ·cm2. Drain-induced channel effects were proposed to explain the change in the gate current at different drain voltages. Drain current decline in the output characteristics and the reverse turn-on between drain and source can be explained by effects. A technological computer-aided design was used to simulate the change of the depletion region and confirm the explanation. Detailed analyses of the channel effects provide a reference for the design of novel structures. The characteristics at different temperatures demonstrated the stability of threshold voltage and specific on-resistance, thus indicating the great potential of applications in switching power circuits of vertical GaN JFETs.

Ultra‐Low Power and Reliable Dynamic Memtransistor Based on Charge Storage Junction FET with Step‐Wise Potential Barrier for Energy‐Efficient Edge Computing Framework

AbstractThe emergence of technologies such as Artificial Intelligence (AI) and the Internet of Things (IoT) has ushered in the era of big data. The demand for low‐power hardware systems and efficient algorithms has become more imperative. In this study, an ultra‐low‐power dynamic memtransistor based on the charge storage junction Field‐Effect Transistor (FET) with a step‐wise potential barrier is developed. A simple yet efficient device structure allows for analog programming and spontaneous relaxation. The device demonstrated fast speed (tens of nanoseconds (ns)) and low current (in picoamperes (pA)), resulting in ultra‐low programming power (in attojoules (aJ)). Furthermore, the device exhibited high reliability, with a 0.4% cycle‐to‐cycle variation and endurance over 107 pulses, owing to its non‐structural destructive operation process. An operation scheme is developed that enables read on/off and program/inhibition mode for 2T (1 memtransistor‐1 selecting transistor) array. The capability to distinguish temporal data using the device's spontaneous relaxation characteristics is demonstrated. A reservoir computing (RC) system framework is constructed using simulation and verified that the dynamic memtransistor can extract features efficiently from a hand‐written digit dataset. It is anticipated that the developed dynamic memtransistor, with its distinctive temporal characteristics, will play a pivotal role in developing a novel low‐power computing framework.

High-responsivity, high-detectivity, broadband infrared photodetector based on MoS2/BP/MoS2 junction field-effect transistor

Sensitivity stands as a critical figure of merit in assessing the performance of a photodetector and can be characterized by two distinct parameters: responsivity or detectivity. Simultaneous optimization of these two parameters is essential to ensure the applicability of a single detector across various scenarios, yet it remains a persistent challenge for mid-infrared photodetector. Here, we demonstrate that the construction of a photoconductive detector based on a MoS2/BP/MoS2 npn junction field-effect transistor configuration can effectively balance the tradeoffs between photoresponsivity and detectivity. In this device, the black phosphorus layer serves as the channel, while the top and bottom MoS2 layers act as photogates to boost the photocurrent. Consequently, a high-performance room-temperature-operating mid-infrared photodetector with a responsivity and detectivity reaching 9.04 A W−1 and 5.36 × 109 cm Hz1/2 W−1 (1550 nm), and 7.25 A W−1 and 4.29 × 109 cm Hz1/2 W−1 (3600 nm) is achieved. Our study provides an alternative structural design, enabling the applications of mid-infrared photodetectors across multiple scenarios.

Thinning Solution‐proceed 2D Te for p‐ and n‐channel Junction Field Effect Transistor with High Mobility and Ideal Subthreshold Slope

AbstractTwo‐dimensional non‐layered tellurene (Te) can serve as a promising candidate in transistor applications because of its high carrier mobility and air stability. However, it is still quite challenging in aspect of ultra‐thin channel and gate‐control ability in conventional metal‐oxide‐semiconductor field‐effect transistor architecture. This work proposes a facile thinning strategy for solution‐proceed Te flakes and fabricates a junction field‐effect transistor (JFET) architecture, that has well addressed the above‐mentioned two issues. Through a mild oxidative thinning process, the post‐growth Te flakes are thinned from bulk to few‐layer, guaranteeing the highly efficient electrostatic doping as a transistor channel. Then, a four‐terminal JFET‐based on p‐Te and n‐ReS2 is designed, achieving a multifunctional integration of rectification diode, p‐ and n‐channel transistor in one single device. By accessing different contact scheme, the ReS2/Te p‐n diode is explored with a rectification ratio of 103, the p‐channel JFET exhibits a high hole mobility of 317.6 cm2V−1s−1, ideal low subthreshold swing of 84 mV dec−1. While the n‐channel JFET is obtained with electron mobility of 67.6 cm2 V−1s−1 and SS of 229 mV dec−1. Both p‐ and n‐channel devices showcase clear saturation characteristic with ultra‐small pinch‐off voltage (≈0.4 V), which is crucial for low‐power logical and integrated circuit applications.

Process-in-Memory realized by nonvolatile Task-Scheduling and Resource-Sharing XNOR-Net hardware Accelerator architectures

Due to the success of artificial intelligence systems in solving complex problems, these systems have been investigated in many applications. There is an increasing demand for these systems in many new applications. The XNOR-Net, a binary neural network, is a promising candidate for implementing these systems in devices with limited power and hardware resources. Efficient hardware implementation of XNOR-Nets is critical and has been widely investigated in recent research. In this paper, a resource-sharing gate and architecture and a task-scheduling gate and architecture have been proposed. To reduce power consumption, the proposed nonvolatile logic-in-memory gates are designed based on the magnetic tunnel junction (MTJ) and carbon nanotube field-effect transistor (CNTFET) devices. Using the proposed resource-sharing gate for hardware implementation of XNOR-Net minimizes the number of flip-flops, power consumption, PDP, and area by at least 75%, 75%, 60%, and 42%, respectively, as compared to its state-of-the-art counterparts. Also, using the proposed task-scheduling design to implement the XNOR-Net on 2, 4, and 8 datasets, the power consumption is reduced by at least 24%, 54%, and 65%, respectively, compared to its state-of-the-art counterparts.

Tunable optoelectronic response in van der Waals heterojunction transistors for artificial visual recognition

Optoelectronic synaptic transistors are advantageous in in-memory light sensing for artificial neural networks. Herein, optoelectronic synaptic junction field-effect transistors (JFETs) based on a Ga2O3/MoS2 heterojunction are fabricated. The devices exhibit robust electrical performances, including a high on/off ratio of 108, a low subthreshold swing of 69 mV dec−1, and a high output current of 3.4 μA μm−1. An inverter and a NAND gate are constructed based on the dual-gated configuration, with the inverter showing a high voltage gain of 28 and the near-ideal noise margin of 90.4%. Additionally, the devices demonstrate outstanding optoelectronic performances benefiting from the strong light–matter interactions of MoS2. Typical synaptic plasticities, including short-term plasticity, long-term plasticity, and spiking-rate-dependent plasticity, are simulated by applying the light pulses. Furthermore, metaplastic excitatory postsynaptic current, metaplastic facilitation of long-term potentiation and transition from potentiation to depression are also readily demonstrated. The artificial neural network, in which neurons are interconnected through our proposed optoelectronic synaptic transistors, achieves a high accuracy of 89.8% in recognizing handwritten digits. This work provides insight into the design of an optoelectronic synapse based on JFETs.