Junction Barrier Schottky Diodes Research Articles

1.38kV Merged Pin Schottky Rectifier for High Power Device Applications

In this paper, we have proposed a modified version of junction barrier schottky diode (JBS) with fused trench structure to enhance electrical properties. The device has an increased current density, low forward voltage drop, high breakdown voltage and large schottky contact area as compared to previous merged pin-junction barrier schottky diode.4H-SiC is used as a substrate and device is purely simulation based. To carry out simulation work Silvaco TCAD(ATLAS) is used. The simulated device has current density of 110 A/cm2 with schottky region having height of 2.5 μm and at a forward voltage drop of 2.5 V. The proposed device has more number of schottky contacts than the previous devices and it reduces the forward voltage drop by 20% at current density of 140 A/cm2. The output capacitance of this device, common JBS and earlier merged pin schottky diode are almost same. Moreover, the forward and reverse features of device are studied at room temperature (25 °C) as well as at higher temperatures.

Heavy Ion Transport Modeling for Single-Event Burnout in SiC-Based Power Devices

SiC power devices have been found experimentally to burn out from heavy ion strikes with linear energy transfers as low as 2.0 MeV $\cdot $ cm2/mg. In this paper, to better understand the failure mechanisms, we study the single-event burnout (SEB) phenomenon using a unified physics model between heavy ion radiation transport and device response. High-fidelity radiation data, generated from a general purpose Monte Carlo N-particle transport code (MCNP6.2), were modeled using a double Gaussian function to take into account both the heavy ion and the delta ray contributions. SiC junction barrier Schottky (JBS) diodes underwent 3-D TCAD electrothermal simulations using the double Gaussian model. This model was compared against other heavy ion models to determine the behavior of the thermal response from a heavy ion strike. The results reveal that there is a more rapid thermal response from models using high-fidelity heavy ion radiation data than approximated models provided by TCAD simulators. Peak temperature results from high-voltage SiC JBS diodes, which agree with the experimental observation of SEBs in SiC power devices.

Research of Single-Event Burnout in 4H-SiC JBS Diode by Low Carrier Lifetime Control

This paper presents the 2-D numerical simulation results of single-event burnout (SEB) in 4H-SiC junction barrier Schottky (JBS) diode by low carrier lifetime control (LCLC) for the first time. We investigate the SEB performance based on an 1800-V JBS structure and find that the most sensitive ion’s strike position is the middle of junction spacing because of the punchthrough of the electric field at anode contact. Then, the SEB hardening mechanism of LCLC is studied in this paper that the double-sided peak electric field can be effectively improved which results in a significantly decrease of maximal temperature. For the incident particle with different linear energy transfer values, we find that the SEB threshold voltage can be substantially enhanced when the carrier lifetime ( $\tau $ ) is under a certain value. In addition, the basic characteristics with LCLC are discussed that the forward and reversed characteristics are hardly affected.

A Physics-Based Compact Model of SiC Junction Barrier Schottky Diode for Circuit Simulation

A physics-based compact model of silicon carbide (SiC) junction barrier Schottky diode for circuit simulation is developed in this paper. The semiconductor physics mechanism in SiC, such as temperature-dependent mobility and incomplete ionization, are considered. The detailed device parameters, including drift region concentration, drift thickness, active area, and Schottky barrier height, are modeled. Then, a datasheet-oriented parameter extraction procedure for the device parameters is presented for three kinds of commercial SiC Schottky diodes with junction barrier structure. The model is implemented in the circuit simulator PSpice. In order to verify this model, the Technology Computer-Aided Design Sentaurus simulation is conducted with the device parameters and physical models, which shows a good agreement with the PSpice simulation.

A 4H-SiC junction barrier Schottky diode with segregated floating trench and super junction

A 4H-SiC Junction Barrier Schottky Diode with Segregated Floating Trench and Super Junction (S-FT SJ JBS) is presented in this paper. By adopting segregated integrated trench and super junction, the high electric field not only focus on the bottom of trench but also gathers in the top of trench and the edge of super junction, therefore the distributions of the high electric field is more uniform, and thus to substantially improve the breakdown voltage (BV). By using the floating trench, the area of schottky contact is enlarged, thus the density of current is increased in the on state, and the specific on-resistance (Ron,sp) of the device is ultimately decreased. The results of simulation show that the BV and Ron,sp of S-FT SJ JBS diode are 1891V and 0.16 mΩ cm2, and the BV is improved by 29.5% and the Ron,sp is decreased by 50% compared with I-FT SJ JBS diode. The Baliga figure-of-merit (BFOM) of S-FT SJ JBS diode is 894 W·cm−2 which is increased by 236.1% compared with I-FT SJ JBS diode.

Performance and Reliability Impacts of Extended Epitaxial Defects on 4H-SiC Power Devices

This work explores the effects of extended epitaxial defects on 4H-SiC power devices. Advanced defect mapping techniques were used on large quantities of power device wafers, and data was aggregated to correlate device electrical characteristics to defect content. 1200 V class Junction Barrier Schottky (JBS) diodes and MOSFETs were examined in this manner; higher voltage 3.3 kV class devices were examined as well. 3C inclusions and triangular defects, as well as heavily decorated substrate scratches, were found to be device killing defects. Other defects were found to have negligible impacts on device yield, even in the case of extremely high threading dislocation content. Defect impacts on device reliability was explored on MOS-gate structures, as well as long-term device blocking tests on both MOSFETs and JBS diodes. Devices that passed on-wafer electrical parametric tests were found to operate reliably in these tests, regardless of defect content.

4H-SiC 1200 V Junction Barrier Schottky Diodes with High Avalanche Ruggedness

A state-of-the art family of 1200 V junction barrier Schottky (JBS) diodes was developed. These devices are highly competitive in switching applications thanks to low specific series resistance (1.8 mΩ.cm2 at current rating) and low capacitive charge (1420 nC.cm-2 at 800 V). A uniform avalanche distribution over the active area combined with an optimized high-voltage termination provides industry-leading UIS capabilities. Stringent reliability tests were performed to meet the qualification requirements for the industrial market.

Accurate Transient Calorimetric Measurement of Soft-Switching Losses of 10-kV SiC mosfets and Diodes

The characterization of soft-switching losses (SSL) of modern high-voltage SiC mosfet s is a difficult but necessary task in order to provide a sound basis for the accurate modeling of converter systems, such as medium-voltage-connected solid-state transformers, where soft-switching techniques are employed to achieve an improved converter efficiency. Switching losses (SL), in general, are typically measured with the well-known double pulse method. In the case of SSL measurements, however, this method is very sensitive to the limited accuracy of the measurement of the current and voltage transients, and thus is unsuitable for the characterization of fast-switching high-voltage mosfet s. This paper presents an accurate and reliable calorimetric method for the determination of SSL using the example of 10-kV SiC mosfet modules. Measured SSL curves are presented for different dc-link voltages and switched currents. Furthermore, a deeper analysis concerning the origin of SSL is performed. With the proposed measurement method, it can be experimentally proven that the largest share of the SSL arises from charging and discharging the output capacitance of the mosfet module and especially of the antiparallel junction barrier Schottky diode.

A charge-based model of Junction Barrier Schottky rectifiers

A new charge-based model of the electric field distribution for Junction Barrier Schottky (JBS) diodes is presented, based on the description of the charge-sharing effect between the vertical Schottky junction and the lateral pn-junctions that constitute the active cell of the device. In our model, the inherently 2-D problem is transformed into a simple but accurate 1-D problem which has a closed analytical solution that captures the reshaping and reduction of the electric field profile responsible for the improved electrical performance of these devices, while preserving physically meaningful expressions that depend on relevant device parameters. The validation of the model is performed by comparing calculated electric field profiles with drift-diffusion simulations of a JBS device showing good agreement. Even though other fully 2-D models already available provide higher accuracy, they lack physical insight making the proposed model an useful tool for device design.

Impact of High-Temperature Storage Stressing (HTSS) on Degradation of High-Voltage 4H-SiC Junction Barrier Schottky Diodes

High-temperature storage stressing (HTSS) experiments were carried out on high-voltage 4H-SiC junction barrier Schottky (JBS) diodes. The effects of the high-temperature (up to 275 °C) storage under air environment on thermal stability of the 4H-SiC JBS are investigated. The electrical parameter shifts for tested diodes after the HTSS were investigated in detail, and related degradation mechanisms have been discussed. It is found that HTSS has no effect on the Schottky barrier height, the ideality factor ( n ), and specific on-resistance ( $R_{{\text{on-sp}}}$ ). However, it was interesting that the breakdown voltage ( $V_{{\text{BR}}}$ ) of the devices was decreased first and then increased as the storage time increased. With the analysis of the SiO2/4H-SiC interface characteristics using metal-oxide-semiconductor structure fabricated simultaneously with the investigated 4H-SiC JBS on the same wafer and technical computer-aided design (T-CAD) simulations, trapped-electrons and holes located at the interface of SiO2/4H-SiC on termination region are identified to be the basic reason causing the degradation of reverse characteristics in the devices.

Optimized Designing to Improve Electrical Characteristics of 4H–SiC Wide Trench Junction Barrier Schottky Diode

Optimized Designing to Improve Electrical Characteristics of 4H–SiC Wide Trench Junction Barrier Schottky Diode

Leakage current reduction of vertical GaN junction barrier Schottky diodes using dual-anode process

The origin of the leakage current of a trench-type vertical GaN diode was discussed. We found that the edge of p-GaN is the main leakage spot. To reduce the reverse leakage current at the edge of p-GaN, a dual-anode process was proposed. As a result, the reverse blocking voltage defined at the leakage current density of 1 mA/cm2 of a vertical GaN junction barrier Schottky (JBS) diode was improved from 780 to 1,190 V, which is the highest value ever reported for vertical GaN Schottky barrier diodes (SBDs).

Compact modeling of SiC Schottky barrier diode and its extension to junction barrier Schottky diode

A compact model applicable for both Schottky barrier diode (SBD) and junction barrier Schottky diode (JBS) structures is developed. The SBD model considers the current due to thermionic emission in the metal/semiconductor junction together with the resistance of the lightly doped drift layer. Extension of the SBD model to JBS is accomplished by modeling the distributed resistance induced by the p+ implant developed for minimizing the leakage current at reverse bias. Only the geometrical features of the p+ implant are necessary to model the distributed resistance. Reproduction of 4H-SiC SBD and JBS current–voltage characteristics with the developed compact model are validated against two-dimensional (2D) device-simulation results as well as measurements at different temperatures.

Micro-Raman spectroscopy applied in crystal structure analysis on the ESD failure mechanism of SiC JBS diodes

This paper propose a novel reliability analysis approach for electrostatic discharge (ESD) stress on 4H-SiC junction barrier Schottky (JBS) diodes using the technology of Micro-Raman spectroscopy. Several conventional analysis are firstly used to determine the failure site after the JBS diodes are destructed by ESD stress, including optical microscope (OM), Photoemission microscopy (PEM) and scanning electron microscopy (SEM). Then, the Micro-Raman spectroscopy is applied to analyze element identification and crystal structure of micro failure site. The analysis reveals that high electric field and high temperature concentrate in the high-voltage termination, resulting in diode burnout and changing the physical microstructure of base SiC. Furthermore, in the micro failure site, 4H-SiC with different Raman spectrum from base 4H-SiC are clearly found, and carbon escapes out from base SiC by combustion, leaving a mixture of amorphous silicon and polysilicon, which is decomposed from the base SiC on the failure surface.

Electrical and noise properties of proton irradiated 4H-SiC Schottky diodes

The current voltage characteristics and the low-frequency noise in high voltage 4H-SiC junction barrier Schottky diodes irradiated with high energy (15 MeV) protons were studied at different temperatures and irradiation doses Φ from 3 × 1012 cm−2 to 1 × 1014 cm−2. Irradiation led to the increase of the base resistance and the appearance of slow relaxation processes at small, V ≤ 0.2 V, and at rather high, V ≥ 2 V, forward voltages. The characteristic times of these relaxation processes ranged from ∼1 μs to 103 s. The exponential part of the current-voltage characteristic was only weakly affected by irradiation. The temperature dependence of the base resistance changed exponentially with temperature with activation energy Ea ∼ 0.6 eV, indicating that the Z1/2 level plays a dominant role in this process. The temperature increase also led to the increase of the ideality factor from 1.05 at 25 °C to 1.1 at 172 °C. At elevated temperatures and high forward voltages V > 2–4 V, the current voltage characteristics tend to be super-linear. It is concluded that at high voltages, the space charge limited current of majority carriers (electrons) and hole injection from the p-n regions play an important role in the formation of the current voltage characteristic. The frequency dependences of noise spectral density S of proton irradiated Schottky diodes have the unusual form of S ∼ 1/f 0.5.

Single-Event Burnout of SiC Junction Barrier Schottky Diode High-Voltage Power Devices

Ion-induced degradation and catastrophic failures in high-voltage SiC junction barrier Schottky power diodes are investigated. The experimental results agree with earlier data showing discrete jumps in leakage current for individual ions and show that the boundary between leakage current degradation and a single-event-burnout-like effect is a strong function of linear energy transfer and reverse bias. TCAD simulations show high localized electric fields under the Schottky junction, and high temperatures generated directly under the Schottky contact, consistent with the hypothesis that the ion energy causes eutectic-like intermixture at the metal–semiconductor interface or localized melting of the silicon carbide lattice.

Effect of trench structure on reverse characteristics of 4H-SiC junction barrier Schottky diodes

We investigated 4H-SiC trench junction barrier Schottky (JBS) diodes from the viewpoints of the tradeoff between the electric field at the Schottky contact interface (Es) and the forward voltage drop, the effect on reduction of reverse leakage current, and the device yield. By calculating Es, we found that the trench JBS structure can make Es one order of magnitude smaller than that of the planar JBS structure, when the bevel angle (θ) is set between 80 and 90°. Moreover, 600 V/50 A trench JBS diodes were fabricated, and their reverse leakage current at 600 V was made 102 times smaller than that of the planar JBS diode by effectively reducing Es. We also found that this reduction in reverse leakage current decreases the number of low breakdown voltage samples below 600 V and improves the yield.

On Developing One-Chip Integration of 1.2 kV SiC MOSFET and JBS Diode (JBSFET)

This paper presents the design, fabrication, and characterization of the SiC JBSFET (junction barrier Schottky (JBS) diode integrated MOSFET). The fabrication of the JBSFET adopted a novel single metal, single thermal treatment process to simultaneously form ohmic contacts on n+, p+ implanted regions, and Schottky contact on the n-4H-SiC epilayer. The presented SiC JBSFET uses 40% smaller wafer area because the diode and MOSFET share the edge termination as well as the current conducting drift region. The proposed single chip solution of MOSFET/JBS diode functionalities eliminates the parasitic inductance between separately packaged devices allowing a higher frequency operation in a power converter.

(Invited) Advances in SiC and GaN Power Device Development and Future Directions

As wide bandgap semiconductors, devices based on SiC and GaN represent critical next-generation medium voltage and high voltage power switch technology. SiC device technology has matured rapidly over the past two decades, owing to advances in substrate quality, a fundamental understanding of epitaxial growth to characterize defects and identify and eliminate performance-limiting defects such as basal plane dislocations, and device breakthroughs such as the junction barrier Schottky (JBS) diode and DMOSFET. While lateral GaN-based HEMT technology has been highly successful for RF power amplifiers and is well-positioned to supersede GaAs-based MMICs, advances in vertical power device technology has been limited due to the lack of high quality native substrates. As large area substrates have become available by hydride vapor phase epitaxy (HVPE) and ammonothermal growth, several fundamental vertical power devices have recently been realized, including Schottky diodes with edge termination, trench MOSFETs, and CAVETs. However, significant fundamental materials challenges currently limit device performance, specifically the realization of repeatable thick drift layers with low background doping as well as a reliable selective area planar process for p-type doping. In this presentation, an overview of SiC and GaN device development at the U.S. Naval Research Laboratory will be summarized, first looking at SiC devices including the development of novel materials characterization techniques to understand the role of defects on device performance, reliability and failure analysis of devices, including BPD kinetics in PiN and MPS diodes, and novel device designs including grayscale termination processes, temperature compensated PiN diodes, and hybrid Si/SiC modules. Recent developments in GaN vertical device technology will also be presented, including the development of an ion implanted p-type doping process and preliminary materials characterization to understand the relationship between substrate quality, epitaxial layer quality, and device performance. Future directions for GaN device development enabled by the availability of bulk substrates will also be discussed, including implications for lateral devices, novel lateral device designs, and fundamental materials work based on the lessons learned from SiC.

(Invited) Vertical GaN Devices Enabled By Selective Area P-Type Doping

A key element for enabling high performance vertical GaN power electronic devices is the capability to realize selective area p-type doping. The ability to arbitrarily define p-type regions through ion implantation eliminates the need for epitaxial regrowth on etched surfaces, which is currently a well-known technological roadblock. However, activation of implanted Mg is also a challenge, since activation of the Mg acceptors requires annealing at temperatures above the thermodynamic stability limits of GaN in atmosphere. Implementing the symmetric multi cycle rapid thermal annealing (SMTRA) technique has been shown to activate up to ~10% of the implanted Mg dopant atoms. This technique includes a temporary thermally stable capping layer, annealing in a nitrogen overpressure, and performing a well-optimized annealing temperature profile including multiple spike anneals. Vertical GaN junction barrier Schottky (JBS) diodes and Schottky barrier diodes (SBDs) with implanted junction termination extension (JTE) are demonstrated using the SMRTA process, as are process module development toward trench MOSFET devices.