Josephson Logic Research Articles

Progress towards innovative and energy efficient logic circuits

The integration of superconductive nanowire logic memories and energy efficient computing Josephson logic is explored. Nanowire memories are based on the integration of switchable superconducting nanowires with a suitable magnetic material. These memories exploit the electro-thermal operation of the nanowires to efficiently store and read a magnetic state. In order to achieve proper memory operation a careful design of the nanowire assembly is necessary, as well as a proper choice of the magnetic material to be employed. At present several new superconducting logic families have been proposed, all tending to minimize the effect of losses in the digital Josephson circuits replacing resistors by adequate combinations of inductors in the logic gates. Among those, the nSQUID concept relies on the propagation of vortices along underdamped Josephson transmission lines. While, in principle, this logic family provides very low dissipation, several issues, such as speed and stability, have yet to be addressed. The current status of design and testing of n-SQUID logic gates and circuits as well as of the design and implementation of the nanowire memories is reported

Defect-oriented testing of Josephson logic circuits and systems

In this paper, defect-oriented testing of low temperature superconducting Josephson logic systems is used as a basis for structural test generation. This requires the investigation of processing defects using defect monitors and the development of fault models. Inductive fault analysis techniques play an important role in this approach. By means of fault injection in the JSIM circuit simulator, the most effective test signals can be derived which can subsequently be used for test-generator hardware in a built-in self test environment.

Towards a 16 kilobit, subnanosecond Josephson RAM

A critical component of ultrahigh-speed Josephson logic systems is compatible memory. We are developing a fast Josephson memory that could be used as a small memory or first-level cache. Performance goals include sub-ns access and cycle time, 16 kbit cm-2 integration scale, low power consumption and appreciable yield. Initial test results on circuits fabricated in TRW's standard Nb integrated circuit process indicate that all these goals may be achieved. A 5 bit parallel decoder and 1 kbit memory array have been tested at 0.5 GHz. The maximum operating frequency of the memory array was limited by the test equipment. Circuit density is consistent with 16 kbit cm-2. The top-level architecture has been chosen to achieve high throughput and low skew. The architecture is word organized, multiported and interleaved.

High-speed testing of Josephson logic circuits by an on-chip signal-pattern generator

Abstract We have developed an on-chip signal-pattern generator (SPG) for high-speed testing of latching-type Josephson logic circuits. The basis of the SPG is using a feedback shift register, in which the complement output of the last-stage LATCH gate (a D flip-flop) is fed back to the first-stage LATCH gate. Since the SPG consists of only LATCH gates and requires no external input signal, the design and high-speed operation are greatly simplified. We performed a high-speed measurement of the 1-bit SPG and found that the SPG has the potential to operate at a speed of more than 4.6 GHz. We also demonstrated a high-speed testing of a 2-bit logic circuit with the 2-bit SPG up to a clock frequency of 1 GHz.

Clock-driven on-chip testing for superconductor logic circuits

We have developed and demonstrated a clock-driven on-chip testing (CDOT) method for high-speed testing of superconductor logic circuits. This testing method uses an on-chip signal-pattern generator (SPG) driven by a clock signal. The SPG is based on a feedback shift register, in which a complement output of the last-stage D-flip-flop is fed back to the first-stage D-flip-flop. Thus, SPG generates a periodic signal-pattern when a clock signal is applied to it. The advantages of this testing method are that: (a) no external control signal is needed; (b) a simple SPG that consists of only D-flip-flops is used; (c) it is easy to extend to multi-bit testing. This greatly simplifies high-speed testing and design of test circuits. We have applied this method to the high-speed testing of the ring interface (RIF) circuit, which is an elemental circuit in our superconducting ring-network system. We have designed a test circuit, consisting of the RIF circuit and a 12-bit on-chip test-pattern generator, with resistor-coupled Josephson logic (RCJL). The test circuit includes about 1,400 Josephson-junctions. It has been fabricated using Nb/AlO/sub x//Nb Josephson-junction technology. As the result of the high-speed testing, full operation of the RIF circuit at 1-GHz clock frequency and proper operation of a sending part of the RIF circuit at 2-GHz clock frequency have been successfully verified.

YBCO SQUIDs fabricated by field-emission electron beam source

We report the applicability of YBa/sub 2/Cu/sub 3/O/sub 7-y/ (YBCO) SQUIDs fabricated by field-emission electron beam source. The junctions show hysteresis and self-resonance steps related to a high frequency resonance in the dc SQUID loop at a voltage V/sub res/=/spl Phi//sub 0//2/spl pi/(LC/2)/sup 1/2/ around 0.3 T/sub c/. The noise spectrum of the SQUIDs was measured with dc-bias schemes at different temperatures and showed values around 10/sup -4/ /spl Phi//sub 0//Hz/sup 1/2/ down to frequencies of 10 Hz at 40 K. The influence of magnetic flux, operating temperatures and flux-voltage transfer factor (|dV/d/spl Phi/|) were investigated. We also tested inverter operation of a dc-biased Josephson logic gate composed of an rf SQUID and a dc SQUID to realize logic circuit performance. Operation of the inverter has been successfully demonstrated although the operating temperature is low, around 10 K.

Hybrid superconducting pixel detector

A new position sensitive cryogenic detector for high energy particles based on Josephson Tunnel Junctions (JTJs) is proposed. This consists of a semiconductive substrate to transduce the energy of particles in charge and of a JTJ as a current driven sample and hold circuit. The possibility of coupling to high-speed Josephson logic families and the sensitivity to magnetic fields are also addressed.

Hybrid Josephson-CMOS FIFO

We describe the design of a hybrid Josephson-CMOS first-in-first-out memory (FIFO) for communications and signal processing applications. The FIFO takes advantage of high speed Josephson logic and dense CMOS memory. We focus on the low power CMOS ring pointer architecture employing a dual-port CMOS SRAM array and illustrate how a high speed Josephson demultiplexor-multiplexor pair can greatly increase throughput. We describe a novel eight transistor dual-port CMOS SRAM cell with low swing write and current-mode read with an asymmetric SQUID to perform differential current-sensing. Finally, we discuss the peripheral Josephson demultiplexor and multiplexor designed in edge-triggered logic.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A DC-powered Josephson logic family that uses hybrid unlatching flip-flop logic elements (Huffles)

This paper describes the development of a dc-powered Josephson logic family that uses hybrid unlatching flip-flop logic elements (Huffles). The Huffle circuit used in this study is modified by adding a parallel resistor to the original Hebard-type Huffle circuit. Analysis of the circuit's operation shows that the undesirable hung-up phenomena are prevented by this modification. Based on the result of the analysis, the circuit's parameters are derived and a typical operating margin of /spl plusmn/26% is obtained. Besides AND/OR operations using a threshold logic operation, two-input exclusive OR (XOR), two-input multiplexor (MUX), and three-input majority (MAJ) operations are realized using a Huffle gate in which 2-Josephson-interferometers (2JI) in the standard Huffle gate are replaced by stacked-2JI's. Thus, a Huffle logic family, formed from NOT, AND, OR, XOR, MUX, MAJ, and flip-flop (FF), are constructed. By using this Huffle logic family, a 6-b arithmetic logic operating unit (ALU), a 6-b analog-to-digital converter (ADC), and a 6-b gray-to-binary converter (GBC) have been successfully operated. During high-speed testing, a 1-b comparator was operated up to an input bandwidth of 6 GHz.

Design and operation of josephson circuits using ruffle gates with a stacked structure

AbstractDC‐powered Josephson logic gates have the advan tage of being free from operation error due to crosstalk from power current in contrast to ordinary ac‐powered Josephson logic gates. One of these, the HUFFLE (hybrid unlatching flip‐flop logic element) gate using stacked Josephson interferometers (JI) can execute complicated logic functions by itself. Therefore, high‐Speed operation of logic circuits using HUFFLE gates may be expected because the number of logic stages in the circuits is reduced. to investigate the improvement in circuit per formance by using HUFFLE gates with the stacked structure, the authors have fabricated a 6‐bit arithmetic logic unit (ALU) and tested its operation. Two new logic gales, exclusive OR and majority, newly developed using the stacked structure have been developed. the ALU which performs the four functions, AND, OR, exclusive OR, and ADD, is realized with seven logic stages. Ac cordingly, reduction in the number of logic stages and execution time of the ALU by use of the stacked HUF FLE gate family is confirmed.

The design for a Josephson micro-pipelined processor

A novel processor with micro-pipelined architecture is proposed for latch-type Josephson logic devices. The processor is segmented into several operating stages activated by a multi-phase power system. Independent register groups are allocated to each stage in order to support pipeline processing of several instruction streams. This architecture allows building of a fine pipeline pitch processor which is capable of MIMD processing. A 12-bit micro-pipelined Josephson processor, containing an ALU, a multiplier and 16 registers, is described. Driven by a 3-phase AC power system, it is able to process 4 instruction streams simultaneously. A pipeline pitch of 3.3 GHz is expected using conventional Josephson device technology. A 4-bit processor design for 12-bit data length is also discussed. >

Niobium based Josephson circuit technology

Abstract Since the introduction of reliable niobium junctions, Josephson circuit technology has made remarkable progress. We have demonstrated high speed Josephson circuits such as a 4-bit microprocessor and an 8-bit digital signal processor. In this paper, we describe key technologies to realize these circuits, mainly from the viewpoint of circuit design. One of them is the high speed modified variable threshold logic (MVTL) gates which have a large operating margin and high sensitivity. Another is the three-phase ac power system. This power method requires no latching circuits, making the circuitry very simple and resulting in high speed operation. For designing large scale circuits, a systematic design method is also important. Josephson logic has latching characteristics and requires alternate current supply that is quite different from semiconductor logic. We modified existing tools for semiconductor circuits and established a new design system. We also introduced scan path registers for testing the circuit. Using two scan path registers, one at the input and one at the output, we demonstrated RAM read out operation.

A speedup method of a high-speed direct-coupled Josephson logic gate

The switching mechanism of a direct-coupled Josephson logic gate, a four-junction logic gate, has been investigated. It was found that a high-speed input signal current is wasted in an input-output separation resistance (R/sub i/). A speedup method has been developed in which an inductance is connected to (R/sub i/) in series. The value of the inductance was found to be five times larger than the effective inductance of the input junction. A speedup of 40% in the gate switching was demonstrated by a logic delay experiment using submicron NbN-MgO-NbN junction technology. The minimum logic delay of 3.0 ps/gate was obtained with fan-out 1.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A 4-kbit Josephson nondestructive read-out RAM operated at 580 psec and 6.7 mW

A fully decoded 4-kb Josephson nondestructive readout high-speed RAM with vortex transitional memory cells was designed and operated successfully. The 4-kb Josephson RAM is composed of 64-b*64-b cells, polarity-convertible drivers, address decoders using resistor coupled Josephson logic (RCJL) gates, and a resistively loaded sense circuit. The memory cells use vortex transitions in their superconducting loops for writing and reading data. The cells are activated by two control signals without timing control, while all peripheral circuits are activated by an AC power supply. This memory configuration eliminates the timing sequence needed for memory operations, resulting in a decrease in the memory operation time for an actual memory chip. The 4-kb Josephson high-speed RAM was fabricated using niobium planarization technique with a 1.5- mu m design rule. The RAM circuit size is 4.8*4.8 mm/sup 2/ and the memory cell is 55*55 mu m/sup 2/. More than 25000 Nb-AlO/sub x/-Nb Josephson junctions with approximately 1200 A/cm/sup 2/ critical current density are contained in the RAM chip. An access time of 580 ps and a power consumption of 6.7 mW are obtained for the nondestructive memory operation.

A new quantum flux parametron logic gate with large input margin

The quantum flux parametron (QFP) is a flux-transfer, flux-activated Josephson logic device which realizes much lower power dissipation than other Josephson logic devices. Being a two-terminal device, its correct operation may be affected by coupling to other QFPs. The problems include backcoupling form active QFPs through inactive QFPs (relay noise), coupling between QFPs activated at different times because of clock skew (homophase noise), and interaction between active QFPs (reaction hazard). Previous QFP circuits worked by wired-majority, which is a linear input logic and has low input margin. A logic gate (D-gate) using a QFP to perform logic operations has been analyzed and tested by computer simulation. Relay noise, homophase noise, and reaction hazard are substantially reduced. Moreover, the inputs have little interaction, and hence input margin is greatly improved. Using only D-gates it is possible to realize any combinational logic function. Important logic functions can be realized using one gate, such as a two-input multiplexer, majority, and parity. Since the QFP has a latching effect, D-gates can realize fully pipelined circuits without additional registers.

Josephson 32-bit shift register

A 32-b shift register designed by edge-triggered gates was tested with +or-25% bias margin and +or-81% input margin for the full array. Simulations showed +or-55% bias margin at 3.3 GHz and worked up to a maximum frequency of 30 GHz with a junction current density of 2000 A/cm/sup 2/, although the shift register has only been tested up to 500 MHz, limited by instrumentation. This edge-triggered gate, consisting of a pair of conventional Josephson logic gates in series, has the advantages of wide margins, short reset time, and insensitivity to global parameter variations.

A 1-GHz-clock Josephson microcomputer system

A 1-GHz-clock Josephson microcomputer system was developed to demonstrate the possibility of a high-speed superconducting computer system. It consists of a 4-b data processor chip and a 1-kb RAM chip. For the fabrication of these Josephson integrated circuits, a cross-shaped Nb-AlO/sub x/-Nb Josephson junction process was developed in order to realize small junction size and improve critical current uniformity, and has made fabrication of LSIs with several thousand gates possible. A latchup-free DC flip-flop is an important element in the high-speed Josephson logic and memory circuits, having been applied to an all-DC-powered Josephson RAM with asynchronous access capability. A low-inductance chip-to-chip carrier is an architectural and design concept for the Josephson computer's 1-GHz-clock operation, suppressing the crosstalk between the AC power and the output signals. Each chip is 7 mm square and is fabricated using a 2.5- mu m-rule Nb-AlO/sub x/-Nb junction process. The chips are connected on a superconducting carrier by solder bumps in a die size of 15 mm by 25 mm. The system is constructed from 8123 Josephson interferometer devices and is operable in a 1-ns cycle with 50-mW power dissipation.

Numerical simulator for superconducting integrated circuits

A numerical simulator for the analysis of Josephson logic circuits that uses numerical methods and dynamic memory allocation, and is capable of simulating a wide variety of superconducting and conventional circuits, is described. The program uses SPICE-like input syntax and is capable of both static and dynamic analysis. The basic operation of Josephson logic is explained and an example simulation is given. >

An all DC-powered Josephson logic circuit

A novel DC-powered Josephson circuit is reported. An improved HUFFLE-type DC flip-flop with a parallel resistor, to prevent hang-up, is constructed by combinational circuits as well as sequential circuits. The basic device is a vertical type two-junction interferometer with only three-metal layers. The design rule is 2.5 mu m. High junction-current density allows for a wide operating margin even with a low inductance load. Basic circuit function test elements have been completed. The DC flip-flop with excess gate current works as a GHz range VCO (voltage controlled oscillator) for internal clock generation. The speedup junction successfully accelerated the switching speed. The ring-oscillator showed a minimum gate delay of 11.3 ps. >

Speed optimization of Josephson direct coupled logic

An advanced design of direct coupled Josephson logic (ADCL) is developped for optimum speed at the circuit level with picosecond superconducting junctions (RN x C = 2 ps ). Each gate consists of an input logic cell and an output buffer (OR gate) which brings efficient standardization. The design minimizes junction turn-on-delay and loading effects to reduce speed degradations in circuit conditions of operation. The methodology of speed optimization with good static and dynamic margins, small dissipation and large integration capability is presented. The new features of the ADCL gate design are, a suppression of the input resistive shunt in OR gate, a large signal line impedance, voltage and current amplification, a standardization of gate design. The maximum gate speeds at bias near threshold (≽ 95 %) are 2.5 ps (OR) and 5 ps (AND). At fan in/fan out ≽ 2 and 80 % of threshold bias giving # ± 20 % operating margins, the gat switching times rise only at 5 ps (OR) and 10 ps (AND) with as little as 3 μW/gate power dissipation. The corresponding power-delay product of the OR gate rates at 15 aJ.