Defect-oriented testing of Josephson logic circuits and systems

Abstract

In this paper, defect-oriented testing of low temperature superconducting Josephson logic systems is used as a basis for structural test generation. This requires the investigation of processing defects using defect monitors and the development of fault models. Inductive fault analysis techniques play an important role in this approach. By means of fault injection in the JSIM circuit simulator, the most effective test signals can be derived which can subsequently be used for test-generator hardware in a built-in self test environment.