Hybrid Josephson-CMOS FIFO

Abstract

We describe the design of a hybrid Josephson-CMOS first-in-first-out memory (FIFO) for communications and signal processing applications. The FIFO takes advantage of high speed Josephson logic and dense CMOS memory. We focus on the low power CMOS ring pointer architecture employing a dual-port CMOS SRAM array and illustrate how a high speed Josephson demultiplexor-multiplexor pair can greatly increase throughput. We describe a novel eight transistor dual-port CMOS SRAM cell with low swing write and current-mode read with an asymmetric SQUID to perform differential current-sensing. Finally, we discuss the peripheral Josephson demultiplexor and multiplexor designed in edge-triggered logic.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>