An ultra high density pseudo dual-port SRAM in 16nm FINFET process for graphics processors

Abstract

In recent times, graphic, audio and video definition has improved due to significant advancement in complex algorithms and video processing techniques. These techniques require heterogeneous and multi-core processors because of their complex computation abilities. Dual-port memories have become an essential component of CPUs because multi-core processors require significant data transfer. However, dual-port memories come at a cost of increased area and leakage. In this paper, an ultra-high-density dual-port SRAM (RADPUHD) architecture is proposed which addresses area and leakage challenges. It is designed and fabricated in 16nm technology. This paper presents use of a single-port bitcell to achieve functionality of dual-port SRAM thus improving area efficiency. The use of latches for Port B signals instead of full flip-flops further reduces area. The proposed design is a bolt-on wrapper around a 6T single-port SRAM. This design achieved a memory density of 8.1Mb/mm2 chip area and achieved 53% area savings and approximately 60% leakage savings when compared to an 8T dual-port SRAM that was also fabricated in 16nm. Silicon results show that the proposed circuit is functional down to a minimum operating voltage of 520mV.